JPH0267735A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a spacer SiO2 with LDD structure from capturing carrier by providing an insulating film on the semiconductor surface between a gate electrode and a drain contact, and forming a conductive layer connected to a drain thereon to obtain parasitic FET structure, and making said insulating film thin enough to be passed through by hot carrier. CONSTITUTION:This structure has no spacer, and an n<+> layer is provided between a channel p<-> layer and a contact part n<+> layer, and a thin insulating film 13, with a thickness not larger than 1000Angstrom through which hot carrier can pass, is provided thereon, and further thereon a conductive layer 14 in contact with a drain n<+> layer is provided. In this construction, a parasitic MOSFET, wherein a gate electrode is in contact with a drain, is formed besides the inherent MOSFET. Thus, the deterioration of the MOSFET due to the hot carrier can be reduced. Further, Vth of the parasitic FET must be lower than Vth of the main FET so that a gate insulating film is made thinner or the concentration or the type of the impurity is changed.

Description

[Detailed Description of the Invention] [Summary] Regarding the structure and manufacturing method of a MOS FET with little operational deterioration, the present invention aims to prevent carriers from being captured by 5iO1 of a spacer in a conventional LDD structure, and an insulated gate. An insulating film is extended on the semiconductor surface between the gate electrode and the drain contact of the type FET, and a conductive layer connected to the drain is formed on the insulating film to provide a parasitic FET structure. The thickness is made thin so that hot carriers can escape.

[Industrial application field]

The present invention relates to a highly integrated semiconductor device and a method for manufacturing the same, and in particular to a MO device with little operational deterioration (reduction in conductance).
Regarding the structure and manufacturing method of SFET.

As semiconductor devices become more highly integrated, even MOSFETs with the LDD structure that have been used in the past have begun to show noticeable deterioration, making it difficult to achieve even higher integration and miniaturization.

[Conventional technology]

Conventionally, a spacer is provided adjacent to the gate, and the impurity profile is set such that the impurity concentration is low in the part immediately below the spacer in contact with the gate and high in the part separated by the spacer to improve the breakdown voltage between the source and drain. This prevents deterioration of the oxide film caused by hot carriers.

Process cross-sectional views of a conventional LDD structure MOS FET are shown in FIGS. 4A-4C.

Refer to Figure 4C.The surface of p-type Si substrate 1 (specific resistance lOΩell) is
Dry oxidation at 00°C to form a 300% oxide film (initial oxidation), then a CVD method to form a 1000% Si3N4 film.
LOCO3 patterning (not shown in Figure A) Using this 5iffN4 film pattern as a mask, perform B ion implantation 50 at eV1xlO+3.
A channel cuttle wall region 2 is formed. LOGOS field oxidation is performed in wet02 to form a 6000 field oxide film 3, and the six Na film and initial oxide film are removed. A gate oxide film 4 is formed by oxidizing the exposed substrate surface. This oxidation is performed under HC1 at 1000° C. to a thickness of 300 μm. Next, after performing vth control 89 ion implantation at 5X10” 60Kev, 5000
Deposition and impurity diffusion of polysilicon 5 is performed, and CVD 5iQ□6 is deposited on it to a thickness of 3000 nm. This 5.6 composite layer is patterned to form a gate electrode.

Phosphorus ions were added to the surface of the semiconductor formed in this way.
0Kev 1 x 10'', and using the gate electrode and field oxide film 3 made of 5.6 as a mask, n
- A layer is formed.

Refer to FIG. 4C. Next, 3000 layers of CVD 5iQ□ 7 are deposited and anisotropically etched to leave sidewalls 8.

As ions are implanted at 50 Kev lXl0''.

Refer to Figure 4 C. After 300 block oxidation, PSG9 was 1 μm thick.
A contact window IO is formed, and A1 is deposited and patterned to form S and D A1 electrodes 11 and 12. Through the above steps, the M of the LDD structure shown in Fig. 4C is
The OSFET is completed.

The drain portion of the conventional LDD structure formed in this manner is shown in an enlarged view in FIG. ing.

However, in this structure, as shown in FIG. 5B, a phenomenon occurs in which hot electrons generated in the channel are captured by the sidewall 5i08 of the spacer as shown by the arrow in the figure, and as a result, the resistance of the n-layer increases. happen.

This degrades the conductance of the FET and creates problems with device reliability.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a structure and a manufacturing method of a semiconductor element that can prevent carriers from being captured by the spacer's sin in the conventional LDD structure.

[Means to solve the problem]

In order to solve the above problems, the present invention extends an insulating film on the semiconductor surface between the gate electrode and the drain contact of an insulated gate FET, and forms a conductive layer on the insulating film to form the main A parasitic FET structure is provided for the FET, and the thickness of the insulating film is made thin so that hot carriers can escape.

The principle of the present invention will be explained using the example shown in FIG. is an insulating film I that is thin enough to allow hot carriers to pass through.
A conductive layer 14 is provided on top of the conductive layer 14, and this conductive layer is brought into contact with the n' layer of the drain. By doing this, in addition to the original MOSFET (main FET), a parasitic MO3FET (drain parasitic FET) whose gate electrode is in contact with the drain is generated.

By providing a parasitic drain FET in this way, the hot carriers alleviate the deterioration of the MOSFET.

Note that in the present invention, the vth of the parasitic FET must be lower than the vth of the main FET.

Possible ways to do this include reducing the thickness of the gate insulating film or changing the impurity concentration or type.

[Effect]

In the MOSFET of the present invention, the conventional LDD structure MO3F
Since the conductive layer 14 of the gate electrode of the parasitic drain FET carries away the hot carriers that cause conductance deterioration, which has been a problem in ET, they do not cause deterioration, and therefore, high reliability can be achieved in fine MO3FET. It is possible to fabricate a gate element.

〔Example〕

A process sectional view of the first embodiment is shown in FIG. 2C.

Refer to FIG. 2C (1) A p-type Si substrate (p 5ub) 1 having a specific resistance of 10Ω1 is prepared.

(2) Perform dry oxidation at 1000° C. to form an oxide film with a thickness of 300 μm (initial oxidation).

(3) Next, CV D Si 3 Na film, film thickness 1
(4) Perform patterning for LOCO3 (the above does not appear in Figure A) (5) B ions are 5QKev, l for channel cut.
Ion implantation is performed under the conditions of Xl013 to form channel cuttle wall region 2.

(6) Next, field oxidation is performed under wet O□ to form a 6000 LOGOS field oxide film 3.

(7) Next, after removing the 3i3N4 film and the initial oxide film, (8) dryoz oxidation is performed at 1000° C. to form a gate oxide film 4 of 300 nm. B for vth control
After performing ion implantation of 60Kev 5 x 10", deposit polysilicon (9) 5. This is C
It is formed to a thickness of 5,000 yen by the VD method, and then impurity diffusion is performed.

(11) After that, polysilicon 5 is patterned to form a gate electrode.

(12) Block oxidation (850° C. dry oxidation: 300 layers grown on a test wafer) is performed. [Thus, the thickness of the oxide film on polysilicon 5 is 500. There will be a total of 450 people on the board].

Refer to FIG. 2C (21) 1,1 ion implantation is performed on the surface to form an n- layer. This is done with 40 Kev ] X I O13.

(22) Next, after forming the contact windows 15 and 16,
(23) Deposition of polysilicon conductive layer 14 by C
The film thickness is 2000 people using the VD method.

(24) Arsenic ion implantation is performed at 50 evl
n' layers are formed on the substrate.

See FIG. 2C (31) Pattern the polysilicon conductive layer 14 (source/drain separation).

(32) Next, dry oxidation is performed at 850°C. At this time, an oxide film of 500 layers is formed on the polysilicon 5.

(33) After that, PSG9 was grown to a thickness of 1 μm, and (
34) Perform flattening melt at 1100°C for 10 minutes.

(35) After forming a contact window on PSG 9,
(36) Aluminum deposition is performed, and (37) aluminum is patterned to form A1 electric scratches 11 and 12.

As described above, the structure shown in FIG. 2C is obtained. The drain structure shown in FIG. 1A is an enlarged view of that part.

If the gate oxide film thickness of the main FET is TI, and the gate oxide film thickness of the drain parasitic FET is T2, then TI
＜'l'. Therefore, in order to lower the vth of the drain parasitic FET, the drain parasitic FET
The substrate concentration of the ET gate is set to n-, making it a depressing type.

Second Example The ion implantation in step (21) in Figure 2B was performed using 40 keν of phosphorus.
2x10", the drain structure as shown in FIG. - is realized and the vth of the enhancement type drain parasitic FET is reduced.

Third embodiment In the second recess, step (12) is performed by etching the gate oxide film,
By drying the block oxidation for 200 minutes at 850° C., the drain structure shown in FIG. 1C is obtained.

As a result, the gate oxide film thickness T2 of the drain parasitic FET is formed to be thinner than the gate oxide film thickness T2 of the main FET, reducing the vth of the drain parasitic FET without changing the substrate concentration. .

Fourth example A fourth embodiment of the present invention is shown in FIGS. 3A-3D.

This utilizes polysilicon sidewalls to realize the structure of the present invention.

See Figure 3C. Steps (1) to (10) are the same as in FIG. 2A.

(11) Form 3000 CVDSiO□.

(12) Perform CV D Si O* and polysilicon patterning.

(13) Block oxidation is done by dry oxidation at 850℃ to a film thickness of 3
Do this for 00 people.

See Figure 3C. (20) Form an n-layer by implanting phosphorus ions.

(21) 4000 person deposition of polysilicon 31 (
22) Perform anisotropic etching to form the sidewall 31'.

(23) Formation of n' layer by A s+ ion implantation at 50K
evIXIO”.

Refer to FIG. 3C (31) Deposit 2000 layers of polysilicon 32 as a conductive layer.

(32) Dope the polysilicon 32 of the conductive layer by As "ion implantation 50 Kev 1 x l O".

(33) The polysilicon 32 of the conductive layer is patterned to separate the source/drain.

Refer to the third diagram (41) Block oxidation is performed by dry oxidation at 900° C. to a film thickness of 300 mm.

(42) Grow PSG 33 to 111m.

(42) Perform flattening melting at 1100°C for 10 minutes.

(43) Form a contact window.

(45) Aluminum deposition (46) Aluminum patterning is performed to form Af electrodes 11 and 12.

By adopting the structure of this embodiment, the sizes of the n-layers of the source and drain can be easily controlled, and stable FET characteristics can be obtained.

The present invention has been described above with reference to embodiments. In the structure of the present invention, the gate insulating film of the drain parasitic FET needs to be formed thin so that hot carriers can tunnel through. The practical limit of its thickness varies depending on the device structure, especially the structure of the drain, but it needs to be thinner than 1000 Å, preferably 500 Å or less,
For example, let's say there are about 250 people. The lower limit of the insulating film thickness is determined by the withstand voltage required of the element. Parasitic F on the drain
Regarding the thickness of the gate insulating film of ET, please refer to the document IEEE ELECT II on gate current of MOSFET.
ON D [! V[CE L[! TTERS VO
L, EDL-7NO, 10,0CTOBER1986,
p, 561-563, or [EEE TRAN
SACTIONS ON [! LECTRON DEV
TC[! S VOL, HD-33No, 10OCTOV
ER1986p, 1529-1533 (see description D).

〔Effect of the invention〕

According to the present invention, compared to the conventional LDD structure MO5FET, the lifespan can be approximately twice as long.
The life here is the time until the conductance value decreases by 10%.

[Brief explanation of the drawing]

1A-C is an enlarged sectional view of essential parts of the first to third embodiments of the present invention, FIG. 2A-C is a process sectional view of the first embodiment of the present invention, and FIG. 3A- D is a process sectional view of the fourth embodiment of the present invention, FIGS. 4A-C are process sectional views of a conventional LDD structure MOS FET, and FIGS. 5A and B are partial cross sections of the drain of a conventional LDD structure MO3FET. It is a diagram. 1 is St substrate 2 is p-type head area with channel cut 3 is field oxide film 4 is gate oxide film 5 is polysilicon, 7 is CV D Si Ot 8 is side wall (Sing) 9 is PSG 10 is contact window 11. 12 shows that the A1 electrode 13 is a thin oxide film 14 that allows hot carriers to pass through, and is a conductive layer (polysilicon). 15. 16 shows that the opening 31 is made of polysilicon 31°. Sidewall (polysilicon) 32 is a conductive layer made of polysilicon. silicon

Claims (1)

[Claims] 1. An insulating film is extended on the semiconductor surface between the gate electrode and the drain contact of an insulated gate FET, and a conductive layer is formed on the insulating film to prevent parasitic effects on the main FET. Target F
1. A semiconductor device comprising an ET structure and an insulating film formed thin enough to allow hot carriers to escape. 2. The semiconductor device according to claim 1, wherein the insulating film has a thickness of 1000 Å or less. 3. The semiconductor device according to claim 1, wherein the parasitic FET is of a depletion type. 4. The semiconductor device according to claim 1, wherein the parasitic FET is of an enhanced type and has a threshold value lower than that of the main FET. 5. The semiconductor device according to claim 4, wherein the gate insulating film of the main FET is formed thinner than the gate insulating film of the parasitic FET, and the impurity concentration of the channel part of the main FET is equal to that of the channel part of the parasitic FET. A semiconductor device characterized by having a higher concentration than an impurity. 6. The semiconductor device according to claim 4, wherein the threshold value is lowered by making the gate insulating film of the parasitic FET thinner than the gate insulating film of the main FET. 7. The semiconductor device according to claim 1, wherein the conductive layer is connected to a drain and also to an external wiring. 8. Following (a) to (f), (a) After forming a thin insulating film on a semiconductor substrate, forming a first conductive layer thereon, and patterning the conductive layer to form a gate electrode. (b) After forming an insulating film to cover the gate electrode, a low concentration impurity layer is formed by ion implantation; (c) An opening is formed in the insulating film on the surface of the semiconductor substrate near the gate. (d) forming a second conductive layer; (e) patterning the second conductive layer to form source and drain lead electrodes; (f) patterning the second conductive layer on the insulating film extending between the electrode and the drain contact window so as to remain connected to the drain extraction electrode; A method for manufacturing a semiconductor device, comprising the step of forming a layer. 9. In the method for manufacturing a semiconductor device according to claim 8, (b)
2. A method of manufacturing a semiconductor device, wherein the step of forming an insulating film to cover a gate electrode is performed after removing portions of the thin insulating film on the semiconductor substrate above the source and drain. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the low concentration impurity layer (b) has the same polarity as the impurity diffused from the extraction electrode (f). Production method. 11. Following (a) to (g), (a) After forming a thin insulating film on a semiconductor substrate, forming a first conductive layer thereon, and patterning the conductive layer to form a gate electrode. (b) forming a low concentration impurity layer by ion implantation after forming an insulating film to cover the gate electrode; (c) forming a second conductive layer; (d) forming the second conductive layer. a step of removing the second conductive layer by anisotropic etching so as to leave a sidewall at least on the drain side of the gate electrode; (e) a step of introducing impurities to form a source and a drain; (f) a source and (g) depositing a third conductive layer after selectively removing the insulating film on the drain; (g) patterning the third conductive layer to form source and drain extraction electrodes; A method for manufacturing a semiconductor device, comprising the step of patterning so that a drain extraction electrode and the sidewall are electrically connected.