JPH0268526U - - Google Patents
Info
- Publication number
- JPH0268526U JPH0268526U JP14884588U JP14884588U JPH0268526U JP H0268526 U JPH0268526 U JP H0268526U JP 14884588 U JP14884588 U JP 14884588U JP 14884588 U JP14884588 U JP 14884588U JP H0268526 U JPH0268526 U JP H0268526U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- channel type
- transistors
- buffer circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案を実施した出力バツフア回路を
示す回路図であり、第２図はその動作を従来例と
比較して示す特性図である。第３図は従来例の回
路図である。
１……電源電圧ライン、２……インバータ、Ｑ
１……第１トランジスタ、Ｑ２……第２トランジ
スタ、Ｑ３……第３トランジスタ、Ｖｉ……入力
電圧、Ｖｏ……出力電圧。
FIG. 1 is a circuit diagram showing an output buffer circuit embodying the present invention, and FIG. 2 is a characteristic diagram showing its operation in comparison with a conventional example. FIG. 3 is a circuit diagram of a conventional example. 1...Power supply voltage line, 2...Inverter, Q
1 ...First transistor, Q2 ...Second transistor, Q3 ...Third transistor, Vi...Input voltage, Vo...Output voltage.
Claims (1)
型の第１トランジスタとＮチヤンネル型の第２ト
ランジスタをＣＭＯＳ接続し、これらのトランジ
スタに共通の入力電圧を印加すると共に第１、第
２トランジスタの接続中点から出力を取り出すよ
うにした出力バツフア回路において、前記第１ト
ランジスタと並列にＮチヤンネル型の第３トラン
ジスタを接続し、前記入力電圧をインバータを介
して前記第３トランジスタに印加するようにした
ことを特徴とする出力バツフア回路。 A P-channel type first transistor and an N-channel type second transistor are connected in CMOS between a power supply voltage point and a reference potential point, and a common input voltage is applied to these transistors, and the voltage of the first and second transistors is In an output buffer circuit configured to take out an output from a connection midpoint, an N-channel type third transistor is connected in parallel with the first transistor, and the input voltage is applied to the third transistor via an inverter. An output buffer circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14884588U JPH0268526U (en) | 1988-11-14 | 1988-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14884588U JPH0268526U (en) | 1988-11-14 | 1988-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0268526U true JPH0268526U (en) | 1990-05-24 |
Family
ID=31420534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14884588U Pending JPH0268526U (en) | 1988-11-14 | 1988-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0268526U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085623A (en) * | 1983-10-17 | 1985-05-15 | Hitachi Ltd | Cmos integrated circuit device |
-
1988
- 1988-11-14 JP JP14884588U patent/JPH0268526U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085623A (en) * | 1983-10-17 | 1985-05-15 | Hitachi Ltd | Cmos integrated circuit device |