JPH0268528U - - Google Patents
Info
- Publication number
- JPH0268528U JPH0268528U JP14839688U JP14839688U JPH0268528U JP H0268528 U JPH0268528 U JP H0268528U JP 14839688 U JP14839688 U JP 14839688U JP 14839688 U JP14839688 U JP 14839688U JP H0268528 U JPH0268528 U JP H0268528U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- frequency
- exclusive
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案になるクロツク変換回路の一実
施例を示す回路図、第２図は第１図の回路の各部
の波形を示すタイミングチヤート、第３図は本考
案のクロツク変換回路をＢＳチユーナに適用した
場合の構成を示す図、第４図及び第５図は従来の
マスタークロツク生成回路の各例を示す図である
。
２１……入力端子、２２……排他的論理和回路
（ＥＸ―ＯＲ回路）、２３，２５……Ｔフリツプ
・フロツプ回路（Ｔ―ＦＦ，）、２４……出
力端子。
Fig. 1 is a circuit diagram showing an embodiment of the clock conversion circuit of the present invention, Fig. 2 is a timing chart showing waveforms of each part of the circuit of Fig. 1, and Fig. 3 is a BS clock conversion circuit of the present invention. FIGS. 4 and 5 are diagrams showing the configuration when applied to a tuner, and are diagrams showing examples of conventional master clock generation circuits. 21...Input terminal, 22...Exclusive OR circuit (EX-OR circuit), 23, 25...T flip-flop circuit (T-FF,), 24...Output terminal.
Claims (1)
る排他的論理和回路と、 この排他的論理和回路の出力を２分周して出力
する第１の分周回路と、 この第１の分周回路の出力を２分周して出力し
、この出力を前記排他的論理和回路の２つの入力
端の他方に供給する第２の分周回路とを備え、 前記第１の分周回路の出力より、前記クロツク
信号の３分の２の周波数の変換クロツク信号を得
ることを特徴とするクロツク変換回路。[Claims for Utility Model Registration] An exclusive OR circuit to which a clock signal is input to one of two input terminals, and a first frequency divider circuit that divides the output of the exclusive OR circuit into two and outputs the divided signal. and a second frequency divider circuit that divides the output of the first frequency divider circuit into two and outputs the divided frequency, and supplies this output to the other of the two input terminals of the exclusive OR circuit, A clock conversion circuit characterized in that a converted clock signal having a frequency of two-thirds of the clock signal is obtained from the output of the first frequency dividing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14839688U JPH0268528U (en) | 1988-11-14 | 1988-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14839688U JPH0268528U (en) | 1988-11-14 | 1988-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0268528U true JPH0268528U (en) | 1990-05-24 |
Family
ID=31419682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14839688U Pending JPH0268528U (en) | 1988-11-14 | 1988-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0268528U (en) |
-
1988
- 1988-11-14 JP JP14839688U patent/JPH0268528U/ja active Pending
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