JPH0268652A - micro computer system - Google Patents

Abstract

PURPOSE:To recover a CPU from runaway at the time of runaway of the CPU from a conventional microcomputer system by providing two control means which send reset signals to each other after the end of the initial processing to perform the initial processing in each other. CONSTITUTION:At the time of normal operation, one CPU 11 performs the initial processing when the reset signal is given to this CPU. Switching signals are sent to signal switches 51a and 61 to which a sensor 4b and a motor 4a are connected, and the sensor and the motor can be controlled by the CPU 11 through input/output interfaces 41 and 51 connected to the CPU 11. The reset signal is outputted to the other CPU 12 to reset the CPU 12. The CPU 12 performs the same operation, and the whole of the microcomputer system is controlled while switching the CPU for the control of the microcomputer system at intervals of a time required for a series of processings. Thus, one CPU is easily recovered from the runaway state to the normal state though falling to the runaway state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system used for controlling machine tools, automobiles, etc., for example.

[Prior Art] Conventionally, a microcomputer system used for controlling machine tools, automobiles, etc. has been configured as shown in FIG. Central processing unit (hereinafter referred to as CP)
(abbreviated as U) 1 includes a read-only storage device (hereinafter referred to as RO).
A read/write storage device (hereinafter abbreviated as RAM) 3, an input interface 4, and an output interface 5 are connected.

The ROM 2 stores programs to be processed by the CPUI and data necessary for the processing.

The RAM 2 is used to store temporary data generated when the CPU performs processing according to a program stored in the ROM 2.

Connected to the input interface 4 are a switch panel 4a for user operation and a sensor 4b such as an encoder of a servo motor 5b. Further, a servo motor 5b is connected to the output interface 5 via a motor drive circuit 5a, and the servo motor 5b is driven according to a control signal output from the CPUI.

[Problems to be Solved by the Invention] However, the above-mentioned microcomputer system may go out of control due to external noise or the like.

This runaway of the microcomputer system is extremely dangerous in, for example, machine tools and automobiles, as it can endanger human life.

Therefore, a watch dog timer 6 as shown in Figure 6 is used to prevent the system from running out of control.
system is being considered. This watch dog timer 6 is a little gable timer. The little gable timer is a timer that, when a new signal is input while the timer is operating, stops the current timer operation and starts a new timer operation. This watchdog timer 6 is activated every time shorter than the time set in the watchdog
Insert the processing program that gives the signal in advance. Then, normally, this watch dog timer 6 is set at regular intervals while the CPU is processing a program.
Since the watch dog timer 6 continues its timer operation, it does not provide a reset signal to the CPUI.

However, when the CPU goes out of control, this watch
Since no signal is given to the dog timer 6, the watch φdog timer 6 gives a reset signal to the CPUI via the OR gate 7 after a preset time from the last time the signal was given, and resets the CPUI. Reset. As a result, the CPUI returns from the runaway state to the normal state.

However, C
There are things that PUI does. In this case, even if a watch dog timer 6 as shown in FIG. 5 is used in the microcomputer system, a reset signal cannot be given to the CPU when the CPU goes out of control, and the CPU
It was not possible to bring I back to normal after it went out of control.

This invention was made in order to solve the above-mentioned problems, and provides a microcomputer system in which the CPU can recover from a runaway when the CPU goes out of control, compared to conventional microcomputer systems. The purpose is to

[Means for solving the problem] The microcomputer system according to the present invention has the following features:
Two control means that each send a reset signal to the other to perform the initial processing after the initial processing is completed, and switching that is controlled by both control means and selectively connects one of the control means and the controlled section. After completing the initial processing, one of the control means that is not connected to the controlled section sends out a heliset signal to the other control means, sends out a control signal to the switching means, and receives the control signal. The switching means disconnects the other control means and the controlled section, and connects the negative control means and the controlled section.

[Operation] During normal operation, one CPU performs initial processing when a reset signal is applied. Then, a switching signal is sent to the signal switch to which the sensor and motor are connected, so that the sensor and motor can be controlled by the aforementioned CPU via the input/output interface connected to the aforementioned CPU. Furthermore, a reset signal is output to the other CPU to reset the other CPU. The other CPU performs the same operation, and the CPU controlling the microcomputer system is switched every time the series of processes described above are performed, and the entire microcomputer system is controlled.

When one CPU goes out of control, a reset signal is given from the other CPU at least after the time for performing the above-mentioned series of processes, so the time during which the entire microcomputer system goes out of control is only a short time. It also becomes easier to return from the current state to the normal state.

[Example] FIG. 1 shows a first example of the present invention. CPU1l includes ROM21, RAM31, input interface 4
1 output terminal, an input terminal of the output interface 51,
One of the input and output terminals of three-state buffer 61 is connected. The ROM 21 stores programs to be processed by the CPU II and data necessary for the processing. RAM31 is CPU II RO
It is used to store temporary data generated when processing is performed according to the program stored in M21.

Further, the ROM 22, the RAM 32, the output terminal of the human interface 42, the input terminal of the output interface 52, and one of the input/output terminals of the three-state buffer 62 are connected to the CPU 12. In ROM22,
A program to be processed by the CPU 12 and data necessary for the processing are stored. Note that the program is the same as that stored in the ROM 21. The RAM 32 is for storing temporary data generated when the CPU 12 performs processing according to a program stored in the ROM 22.

A switch panel 4a for a user to operate the microcomputer system and a sensor 4b such as an encoder of a servo motor 5b are connected to input terminals of the human power interface 41, 42.

Further, from the output terminal of the output interface 51 to the CP
It is connected to the reset terminal of U12 via an OR gate 72, and from the output terminal of the output interface 52
It is connected to the reset terminal of PUII via an OR gate 71. The output terminals of a reset circuit (not shown) are connected to the remaining input terminals of each OR gate 71, 72. Further, the output terminals of the output interfaces 51 and 52 are respectively three-state buffers 51a.
, 52a. A motor drive circuit 5a for driving a servo motor 5b is connected to the output terminals of the three-state buffers 51a and 52a.

A control terminal of the three-state buffer 61 is connected to an output terminal of the output interface 51, and a control terminal of the three-state buffer 62 is connected to an output terminal of the output interface 52. Both three
The other input/output terminals of the state buffers 61 and 62 are
It is connected to RAM33.

Note that the three φ state buffers 51a, 52a, 6
1.62 is an element in which whether or not an input signal is output to an output terminal is controlled according to a given control signal.

The operation of this embodiment will be explained with reference to FIG.

FIG. 2 is a flowchart of processing performed by CPU II immediately after power is turned on. FIG. 3 is a flowchart of the processing performed by the CPU II and the CPU 12. When the micro e-computer system of this embodiment is powered on, the micro e-computer system also:
The CPU II is set to start operating whenever the reset switch of the panel switch 4a is pressed, and immediately after the power is turned on, the CPU II first performs initial processing in step S1. Next, in step S2, the CPU II applies a signal to the control terminals of the three-state buffers 51a and 61 to make both the three-state buffers 51a and 61 conductive. Therefore, the CPU 11 is in a state where it can give a control signal to the motor drive circuit 5a via the output interface 51 and the three-state buffer 51a, and is also in a state where it can read and write data to the RAM 33. become. Furthermore, C.P.
The UII provides a reset signal to the CPU 12 via the output interface in step S3.

Then, in step S4, the CPU II transfers the program and data stored in the ROM 21 to the switch panel 4.
The servo motor 5b is controlled via the motor drive circuit 5a based on the signal from the sensor 4a and the sensor 4b, and the status of the operation is written into the RAM 33 at every minute time.

On the other hand, the CPU 12 that has been given the reset signal operates according to the flowchart in FIG. 3, and performs initial processing in step S5. During this initial processing, the three-state buffers 52a and 62 are in a non-conductive state because no control signal is applied to them. After the initial processing is completed, the CPU 12 applies signals to the control terminals of the three-state buffers 52a and 62 in step S6 to control both the three-state buffers 5.
2a and 62 are brought into conduction. Therefore, the CPU 2 is in a state where it can give a control signal to the motor drive circuit 5a via the output interface 52 and the three-state buffer 52a, and is also in a state where it can read and write data to the RAM 33. become. Further, the CPU 12 provides a reset signal to the CPU II in step S7. Then, in step S8, CPU1
2 reads the status of the operation written in the RAM 33, takes over the operation immediately before the CPU II was given the reset signal, controls the servo motor 5b via the motor drive circuit 5a, and updates the operation every minute. Write status to RAM 33. The CPU 11 to which the reset signal is applied operates in accordance with the flowchart shown in FIG. 3 in the same manner as the CPU 12 described above.

In this way, the entire microcomputer system is controlled while the CPU II and the CPU 12 are switched at each time to perform the series of processes described above.

During this control, if the CPU II or CPU 12 goes out of control, a reset signal is given from the CPU 12 or CPU 11 at least after the time for performing the series of processes described above, so the time when the entire microcomputer system is out of control is It will take a while, and it will be easier to recover after going out of control.

Next, a second example will be described. FIG. 4 shows its electrical configuration. The same parts as in the first embodiment are given the same numbers, and detailed explanation thereof will be omitted. The difference from the first embodiment is that an output interface 51 is connected to the reset terminal of the CPU 12 via an OR gate 72.
It is further connected to an OR gate 73. and,
Further OR from the output interface 52 connected to the reset terminal of the CPU 11 via the OR gate 71.
Connected to gate 73. And OR gate 73
is connected to the watch dog timer 6. Furthermore, watch dog timer 6 is connected to OR gate 71 and OR gate 72.

The flow chart of the processing performed by the CPU II and the CPU 12 is the same as in the first embodiment, and is as shown in FIGS. 2 and 3. During normal operation and CPU11 or CPU12
The operation when either one goes out of control is the same as in the first embodiment.

However, both CPU II and CPU12
When the timer goes out of control, the watch dog timer 6 will not be given any data. Therefore, for a certain period of time (CP
If the watchdog timer 6 gives a reset signal to the CPU 11 and the CPU 12 after the time (longer than the time required for the initial processing operation by the UII and the CPU 12) has elapsed, the watchdog timer 6 will be activated when both the CPUs, the CPU II and the CPU 12, go out of control. will also be able to recover from a runaway state.

Although it is assumed that the contents of the ROM 21 and the ROM 22 are the same, the contents may be different from each other as long as they perform the same processing. Further, if there is no need to hold status for each minute operation, the three-state buffer 61, three-state buffer 62, and RAM 33 are not necessarily required.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a microcomputer system in which the CPU can recover from a runaway when the CPU goes out of control, compared to conventional microcomputer systems.

[Brief explanation of the drawing]

FIG. 1 is an electrical configuration diagram of a microcomputer system according to a first embodiment of the present invention, and FIGS.
The figure is a flow chart of its operation. Figure 4 is the second
1 is an electrical configuration diagram of a microcomputer system according to an embodiment of the present invention. FIG. 5.6 is an electrical configuration diagram of a conventional micro Φ computer system. In the figure, 11.12 is a central information processing unit, 51.52 is an output interface, and 71.72 is an OR gate.

Claims (1)

[Claims] 1. Two control means that each send a reset signal to the other to perform the initial processing after the initial processing is completed, and one of the control means and the controlled section is controlled by both the control means. and switching means for selectively connecting the control means, and one of the control means not connected to the controlled section sends a reset signal to the other control means after completing the initial processing, and also sends a control signal to the switching means. A microcomputer system characterized in that the switching means that receives the transmitted control signal disconnects the other control means and the controlled section, and connects the one control means and the controlled section.