JPH0270437U - - Google Patents
Info
- Publication number
- JPH0270437U JPH0270437U JP15024088U JP15024088U JPH0270437U JP H0270437 U JPH0270437 U JP H0270437U JP 15024088 U JP15024088 U JP 15024088U JP 15024088 U JP15024088 U JP 15024088U JP H0270437 U JPH0270437 U JP H0270437U
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- lead frame
- lead
- recess
- electrode terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の平面図、第２図は
本考案によるリードフレームを使用した半導体装
置組立における電気的特性測定を説明するための
断面図、第３図は従来のテープキヤリア方式のリ
ードフレームの平面図、第４図は従来のテープキ
ヤリア方式による半導体装置組立における電気的
特性測定を説明するための断面図である。
１……絶縁性フイルム、２……スプロケツトホ
ール、３……リード、３ａ……先端部、３ｂ……
電極用端子、３Ｃ……凹部、４……デバイスホー
ル、５……半導体素子、６……探針。
Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a sectional view for explaining electrical characteristic measurement in semiconductor device assembly using the lead frame of the present invention, and Fig. 3 is a conventional tape carrier. FIG. 4 is a cross-sectional view for explaining electrical characteristic measurement in semiconductor device assembly using the conventional tape carrier method. 1... Insulating film, 2... Sprocket hole, 3... Lead, 3a... Tip, 3b...
Electrode terminal, 3C... recess, 4... device hole, 5... semiconductor element, 6... probe.
Claims (1)
ためのデバイスホールが一定間隔で設けられ、前
記絶縁性フイルムに密着して導電性のリードが設
けられて成るリードフレームにおいて、前記リー
ドの電極用端子に凹部が形成されていることを特
徴とするリードフレーム。 In a lead frame comprising a band-shaped insulating film, device holes for mounting a semiconductor element are provided at regular intervals, and conductive leads are provided in close contact with the insulating film, a recess is provided in an electrode terminal of the lead. A lead frame characterized by being formed with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15024088U JPH0270437U (en) | 1988-11-17 | 1988-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15024088U JPH0270437U (en) | 1988-11-17 | 1988-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0270437U true JPH0270437U (en) | 1990-05-29 |
Family
ID=31423205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15024088U Pending JPH0270437U (en) | 1988-11-17 | 1988-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0270437U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325739A (en) * | 2012-03-23 | 2013-09-25 | 南茂科技股份有限公司 | Semiconductor package substrate |
-
1988
- 1988-11-17 JP JP15024088U patent/JPH0270437U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325739A (en) * | 2012-03-23 | 2013-09-25 | 南茂科技股份有限公司 | Semiconductor package substrate |
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