JPH02746U

JPH02746U -

Info

Publication number: JPH02746U
Application number: JP7900288U
Authority: JP
Priority date: 1988-06-15
Filing date: 1988-06-15
Publication date: 1990-01-05

Description

[Brief explanation of the drawing]

第１図は本考案によるゲートアレイの一実施例
の内部ロジツク領域を模式的に示す平面図、第２
図は第１図を部分的に拡大して示す平面図、第３
図、第４図及び第５図はそれぞれ第１図例に適用
される基本セルを模式的に示す平面図、第６図、
第７図及び第８図はそれぞれ第１図例における配
線領域の幅を示す平面図、第９図は従来のゲート
アレイの一例の内部ロジツク領域を模式的に示す
平面図、第１０図は第９図例における基本セルを
模式的に示す平面図、第１１図は従来のゲートア
レイの他の例の内部ロジツク領域を模式的に示す
平面図、第１２図は第１１図例における基本セル
を模式的に示す平面図である。１……内部ロジツク領域、４……ＰｃｈＴｒ、
５……ＰｃｈＴｒ列、６……ＮｃｈＴｒ、７……
ＮｃｈＴｒ列、８，９，１６，１７……基本セル
、１８……マクロセル、１９……マクロセル化さ
れたマクロフアンクシヨンセル。 FIG. 1 is a plan view schematically showing the internal logic area of an embodiment of the gate array according to the present invention;
The figure is a partially enlarged plan view of Figure 1; Figure 3 is a partially enlarged plan view of Figure 1;
4 and 5 are a plan view schematically showing the basic cell applied to the example in FIG. 1, FIG. 6, and FIG.
7 and 8 are plan views each showing the width of the wiring area in the example shown in FIG. 1, FIG. 9 is a plan view schematically showing the internal logic area of an example of a conventional gate array, and FIG. FIG. 9 is a plan view schematically showing the basic cell in the example, FIG. 11 is a plan view schematically showing the internal logic area of another example of the conventional gate array, and FIG. 12 is a plan view schematically showing the basic cell in the example in FIG. FIG. 2 is a schematic plan view. 1... Internal logic area, 4... PchTr,
5...PchTr row, 6...NchTr, 7...
NchTr column, 8, 9, 16, 17... Basic cell, 18... Macro cell, 19... Macro function cell converted into a macro cell.

Claims

[Scope of utility model registration request]

A gate array in which two rows of transistors each consisting of transistors of one conductivity type and transistors arrays consisting of transistors of another conductivity type are alternately and consecutively arranged in an internal logic region.