JPH0276400U

JPH0276400U -

Info

Publication number: JPH0276400U
Application number: JP15475488U
Authority: JP
Priority date: 1988-11-30
Filing date: 1988-11-30
Publication date: 1990-06-12

Description

[Brief explanation of the drawing]

第１図は本考案に係るメモリ試験機能付きＲＯ
Ｍ・ＩＣの一実施例を示すブロツク図、端子接続
図、第２図は同実施例の端子接続図、第３図は同
実施例の動作モード表を示す図である。１：動作モード制御回路、２：Ｙデコーダ、３
：Ｘデコーダ、４：入出力バツフア、５：Ｙ選択
、６：メモリセルアレイ、７：ＣＲＣ演算回路、
８：ＣＲＣデータ保持メモリ、９：アドレス発生
回路、１０：照合回路。 Figure 1 shows an RO with memory test function according to the present invention.
FIG. 2 is a block diagram and terminal connection diagram showing one embodiment of the M-IC, FIG. 2 is a terminal connection diagram of the same embodiment, and FIG. 3 is a diagram showing an operation mode table of the same embodiment. 1: Operation mode control circuit, 2: Y decoder, 3
:X decoder, 4: input/output buffer, 5: Y selection, 6: memory cell array, 7: CRC calculation circuit,
8: CRC data holding memory, 9: Address generation circuit, 10: Verification circuit.

Claims

[Scope of utility model registration request]

In addition to the circuit block including the memory cell array constituting the ROM, there is also a CRC operation circuit that performs a CRC operation on data in the memory cell array, and a CRC operation circuit that performs a CRC operation on data in the memory cell array.
a CRC data holding memory that stores data computed by the arithmetic circuit as CRC data; an address generation circuit that sequentially reads out the data stored in the memory cell array for the CRC arithmetic circuit to compute; and the address generation circuit. A ROM-I with a memory test function, characterized in that it is equipped with a collation circuit that collates the CRC data stored in the CRC data holding memory with the data successively retrieved by the CRC calculation circuit.
C.