JPS60201595A - Storage device for ease of check - Google Patents

Abstract

PURPOSE:To realize a ROM which detects a 2-bit fault as well as 1-bit fault having the capability of the self-test by adding an address counter, a parallel serial converter and a cyclic code check circuit to a ROM and setting an m-bit (m is the number of order of generation polynomial of cyclic code) of the final position of the ROM to a proper value. CONSTITUTION:A flip-flop 30 acts to store a data for a clock cycle's share of one bit. Further, an exclusive OR33 checks that a data transmitted at present is an inverted data of the data of one bit before (however, the initial value of a flip-flop 30 corresponds to ''1'') and if not, the OR33 sets ''1'' to a flip-flop 31. Thus, when the flip-flop 30 is set to ''1'', it shows that the data of a cyclic code check circuit is not 01...01. If one-bit or 2-bit fault exists in the ROM, the pattern is not 01...01. That is, the fault like this is detected easily.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a self-testable memory device, particularly a fixed memory device (hereinafter referred to as RO).
(referred to as M).

[Background of the invention]

ROM failure testing has been performed by reading all the data stored therein and comparing the data with correct values. If a self-testable ROM were to be realized using this method, the capacity of the ROM would be twice as large. In other words, an original ROM and a ROM for storing correct values are required, and in order to make the ROM capable of self-testing, these must be placed on the same integrated circuit. This results in increased hardware size.

As a way to solve the above problem, the 1981 l5S
CC (International 5olid 5t
MISR (Multi Input Sig+1a
tureRegister) has been proposed (1983ISSCCDigest of pap
ers pp, 176-17g) However, this method cannot completely detect 2-bit failures in the ROM.

[Purpose of the invention]

An object of the present invention is to provide a self-testable ROM that can detect not only 1-bit failures but also 2-bit failures.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is an example of a self-testable ROM embodying the present invention. °Here, 1 is the address counter, 2 is the ROM
Main body, 3 is a parallel-to-serial converter, 4 is a cyclic code check circuit, 5 is a control circuit, 6 is an output terminal of the cyclic code check circuit, 7 is RO
8 is a terminal for inputting a signal to start the fault test; 9 is for making it possible to take out the result of the fault test from the terminal 6; 10 is a clock signal input terminal, and 11 to 14 are control signals.

FIG. 2 is a time chart for explaining in detail the present invention shown in FIG. Here, 15 is a clock signal input from terminal 10, 16 is a failure check start signal input from terminal 8, 17 is a signal for incrementing address counter 1, and 18 is a signal for reading from ROM and for parallel/serial converter 3. 19 is a signal that enables the operation of the cyclic code check circuit 6; 20 is a signal that is input from the terminal 9, and is a signal that causes the cyclic code check circuit to serially output data to the terminal 7; 1, 11 corresponds to the signal 17, 12 corresponds to the signal 18, 14 corresponds to the signals 19 and 20, and 13 is a shift clock, which is the same as the input clock 15.

The operation of the circuit of FIG. 1 will be explained below. First, when the failure start signal 16 is input, the address counter 1 and the cyclic code check circuit are initialized, and the control circuit 5 also starts operating. When the control circuit starts operating, a read signal 18 is issued from the control to the ROM2, and the ROM
data is loaded into the shift register in the parallel-to-serial converter 3.

This loaded data is sent to the cyclic code check circuit 4 as serial data by the clock 15.

In order for the data in ROM2 to be sent to the cyclic code check circuit 4 without duplication or interruption, the ROM
2 must be read every N clock cycles.

Here, N is the number of bits of parallel output of the ROM. Therefore, the ROM2 read signal 18 is issued every N clock cycles. In addition, in FIG. 2, N=4. Furthermore, in order to read data at all addresses in ROM 2, address counter 1 outputs test start signal 1.
6, and is then incremented by one by a signal 17 of N clock periods.

This increment operation is executed by the number of W words, which is the capacity of ROM2.

In the manner described above, the data in the ROM is converted into serial data of NXW bits and input to the cyclic code check circuit 4. Regarding the cyclic code check circuit, for example, see Hiroshi Miyayo et al.
The generator polynomial used here is assumed to satisfy the following conditions, although the explanation is omitted here because it is described in detail in "Coding Theory" (Shokodo).

Condition: The generator polynomial is a primitive polynomial, and its degree is m, and m satisfies 2''-1<NXW.Here,
NXW is the total number of bits of data in the ROM.

If the generating polynomial of the cyclic code check circuit 4 satisfies the above conditions, it is possible to detect any two-bit failure in the ROM.

For example, if the ROM has a configuration of 10 bits x 1024 words, the total number of bits in the ROM is 10,240. At this time, if m = 14, 2-1 = 1638
3, so the condition is satisfied. Therefore, since the primitive polynomial of degree 14 is X''440xx'+x+1, this can be used as the generating polynomial of the cyclic code checking circuit 4.

Next, a method for detecting a ROM failure in the cyclic code checking circuit 4 will be described. The simplest method is to serially read out the data remaining in the shift register of the cyclic code check circuit 4 to the outside by inputting the signal 20 in FIG. 2 after completing the failure test. This is then serially compared with the correct value. Since serial comparison is performed, the comparison circuit is simple. Note that in Figure 2, signal 20 is activated for only 5 clock cycles, but in reality, an m-bit shift register corresponds to the m-th order generator polynomial, so in order to read it out, requires at least m clock cycles. This method requires the effort of storing the correct value that should remain in the shift register of the cyclic code checking circuit externally and comparing it with the actually obtained value.

To simplify this effort, it is necessary to set all correct values to O
(or all 1) is sufficient. In this case, an external comparison check is easy. However, in this case,
Since only an O (or 1) signal is output from the terminal 6 in FIG. 2, if this terminal is stuck at 0 (or 1), the failure cannot be detected.

To avoid this, the correct value is 01...01(0
1). This makes it easy to check outside, and it is also possible to detect stuck-at terminal faults. Of course, in order for 01...01 to remain in the shift register of the cyclic code check circuit 4, the last m bits of the ROM must be appropriately determined so that the 01...01 remains in the shift register of the cyclic code check circuit 4. In the example of a 1024-word ROM, the generator polynomial was of degree 14, so by putting an appropriate value in the 14-bit data, that is, the last two words, the value remaining in the shift register of the cyclic code check circuit is 01... Set it to 01.

FIG. 3 shows an external circuit that checks whether the contents of the cyclic code checking circuit are 01...01. Here, 30.
31 is a D type FF, 33 is an exclusive OR circuit, and 34 is an AND (AND) circuit.

Further, cyclic code data is serially input to the terminal 35 (terminal 6 in Figure 1 is connected), and a clock signal (terminal 10 in Figure 1, signal 15 in Figure 2) is input to 36. Ru. Furthermore, a signal (terminal 9 in FIG.
, the same as the signal 20 in FIG. 2), and an initialization signal (same as the terminal 8 in FIG. 1 and the signal 16 in FIG. 2) to the terminal 38.

In FIG. 3, flip-flop 30 has the function of holding data for one bit of clock cycle. In addition, the exclusive OR 33 is the data that the currently sent data is always inverted from the previous bit (however, the data sent from the flip-flop 30
(corresponds to the initial value of 1), and if
If not, immediately flip flop 3
Set 1 to 1. Therefore, flip-flop 3
If I is set to 1, it indicates that the data of the cyclic code check circuit is not 01...01.

Generally, to compare m bits of data, m exclusive OR circuits as well as m flip-flops are required, so the check circuit shown in FIG. 3 can be said to be a very simple circuit.

By the above means, data of NXW bit of ROM is m
Compressed into bit data. Moreover, since this m-bit data has a simple form of 01...01, it can be easily checked whether it matches this pattern or not. Then, 1 bit or 2 bits are stored in the ROM.
If there is a bit failure, this pattern will be 01...Ol.
do not become. This means that such failures can be easily detected.

〔Effect of the invention〕

According to the present invention, an address counter, a parallel-to-serial converter, and a cyclic code checking circuit are added to the ROM, and the last m bits of R and OM (m is the degree of the cyclic code generating polynomial) By setting 0 to an appropriate value, it is possible to realize a self-testable ROM that can detect not only 1-bit but also 2-bit failures.

[Brief explanation of the drawing]

FIG. 1 shows a self-testable RO configured according to the present invention.
An example of an M circuit, Figure 2 is the self-testable ROM of Figure 1.
5 is a time chart illustrating the operation of the circuit. Figure 3 shows the circuit used in the circuit of Figure 1.

Claims (1)

[Claims] 1. In a memory device realized by a semiconductor integrated circuit, an address counter capable of indicating all addresses of the memory device, a parallel-to-serial converter to which data output of the memory device is input, and the parallel to serial converter to which data output of the memory device is input. 1. An easily testable storage device comprising a cyclic code test circuit to which the serial output of a serial converter is input. 2. In the testable storage device described in item 1, when all the data is input to the cyclic code checking circuit as continuous serial data by the parallel-to-serial converter, the shift register in the cyclic code checking circuit An easily testable storage device characterized in that specific data is stored at a specific address of the storage device so that the data pattern is a repeating pattern of 0, 1 or 1, 0.