JPH027736A - Bit phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten time from the detection of a phase difference till the settling by combining 4 clock signals and 4 delay circuits. CONSTITUTION:Two clock signals among 4 clock signals CLK1-CLK4 whose duty ratio is 50%, with equal period and whose phase is deviated sequentially by 1/4 period each are latched respectively by flip-flops(FF) 1, 2 and one clock signal among the 4 clock signals is selected by a selector 3 by the combination of the latched clock signal level. Then the clock signal is used to branch the input signal latched by the FF 4 into four ways, they are inputted respectively to 4 delay circuits 5-8, each delay circuit retards the input signal by a delay time corresponding to the phase difference between the reception side clock and the its own corresponding clock signal set in advance, and a selector 9 selects the output of one relevant delay circuit according to the combination of the output of the FF 1, 2. Thus, the constitution is simplified and the circuit is made stable in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit phase synchronization circuit, and more particularly to a bit phase synchronization circuit in a communication path device of an exchange.

[Conventional technology]

Conventionally, this type of bit phase synchronization circuit has synchronized the input signals by adjusting the phase of each input signal in order to reproduce the signals input at different phases according to the same clock.

FIG. 5 is a block diagram showing a conventional example of a bit phase synchronization circuit, and FIG. 6 is a diagram illustrating data acquisition with respect to the clock signal CLK0 in the conventional example of FIG.

The input signal D in is input to the changeover switch 55 from each stage of the buffer array 54 provided for setting the delay time. The changeover switch 55 switches and connects the input signal D in in accordance with the control signal Sc. Three flip-flops 51, 52, and 53 have their respective data input terminals connected in parallel to the output side of the changeover switch 55, and the clock number 8 CL input to each clock terminal C. At the rising edge of , the data input from each data input terminal is latched, and the captured values S, , S2 are output from the Q terminal.
．． It is output as S3. In addition, the flip-flop 52
and 53 clock signal CL. are shifted in phase from the preceding flip-flops 51 and 52 by a delay time due to delay circuits 56 and 57. Further, the fetched value S2 of the flip-flop 52 is simultaneously output as the output signal D out
It is said that

Therefore, when the input signal D in is input, a control circuit (not shown) compares the captured values S1 and Sj and calculates 5I.
=53, it is determined that the input signal D in and the clock signal CLK0 are phase synchronized, and the captured value S2 is output as the reproduced output signal D out. 5
In the case of If-83, the changeover switch 5 is set by the control signal Sc.
5 to give the input signal D in a delay of each constant value sequentially.

I try to repeat this until I reach Sj.

(See, Proc, InLernaLional
7. urich Sem1naron Dig
Ital Communications, +9
86. C4,1-C4,4) [Problem to be Solved by the Invention] In the conventional example described above, the input signal D in is delayed one by one until the values taken in by the flip-flops 51 and 53 become S, = S3. Due to the configuration that changes the value, the configuration of the phase difference detection circuit and optimal delay value setting circuit becomes complicated, and the delay time of the input signal must be set so that S, = S3 each time, so it is necessary to detect the phase difference. If it takes some time to stabilize the input signal, and the input signal that was stable and synchronized with the clock becomes out of synchronization with the clock due to the influence of noise, etc., the delay value of the input signal should be adjusted each time so that 51 = S3. The disadvantage is that it must be configured.

(Means for Solving the Problems) The bit phase synchronized circuit according to claim 1 of the present invention has four circuits having an occupancy rate of 50%, equal river light, and phases shifted in order by the belonging light. clock signal supply means, and two clock signals out of the four clock signals whose phase is shifted by 1/4 period to the respective data input terminals,
In addition, an input signal having timing information is input to each clock terminal, and the signal level σF of the input signal is
First and second flip-flops that latch clock signals input at the time of a rising or rising edge, four clock signals, and two latched clock signals output from the first and second flip-flops. There is a one-to-one correspondence between the four states based on the combination of high and low levels of the clock signal.
a first selector that selects a corresponding clock signal from among four input clock signals according to a combination of output levels of the two flip-flops; Inputting the clock signal output from the first selector into the input terminal and inputting the clock signal output from the first selector into the clock terminal,
a third flip-flop that latches the input signal when the clock signal rises or γ falls, and the output of the third flip-flop is branched into four and inputted respectively, and four clocks are input. 4 delay circuits that delay the input output of the third flip-flop by 8 times, corresponding to each signal, and 4 delays by the phase difference between each corresponding clock signal and the clock on the receiving side. A one-to-one correspondence is set between the output of the circuit and the four states based on the combination of high and low levels of the two clock signals output from the first and second flip-flops, and the outputs of the two flip-flops Depending on the combination of levels, the corresponding one from among the outputs of the four input delay circuits is selected.
and a second selector for selecting outputs.

The thing of claim 2 is the thing of claim 1, and the first and second
The input terminal of the clock terminal of the flip-flop has means for permitting input of an input signal to the clock terminal only when a setting permission signal is input from the outside.

The third aspect of the present invention is the first flip-flop, which is installed on the data input terminal side of each of the first and second flip-flops, and receives the four clock signals at the data input terminals with a phase difference or period difference. a multi-stage shift register that receives two clock signals, respectively, and latches and shifts the input clock signal every rising or falling edge of the supplementary input signal input to the clock terminal; The first or second flip-flop is installed at the input terminal of the clock terminal of each of the two flip-flops, and only when the outputs of each stage of the multi-stage shift register match and is permitted by the supplementary setting permission signal, Each of the flip-flops has means for latching the input from the supplementary multi-stage shift register.

[For production]

The present invention inputs four clock signals whose phases are sequentially shifted by 1/4 period at an occupancy rate of 50% to a first selector,
Two of the four clock signals are latched by the first and second flip-flops when the signal level of the input signal rises or if-F, and the latched clock signal level is The corresponding one clock signal is selected from the four clock signals based on the combination of the following. Next, the input signal latched using this clock signal is split into four branches, each input to four delay circuits,
Each delay circuit delays the input signal by a delay time corresponding to the phase difference between its own corresponding clock signal and the receiving clock, and the second selector delays the input signal in the same manner as the first selector. By selecting the output of one delay circuit corresponding to 1'' according to the combination of the outputs of the first and second flip-flops, it is possible to output an output signal synchronized with the clock on the receiving device side.

According to a second aspect of the present invention, in the first aspect, one clock signal is outputted once by using input signal input permission means installed at the clock terminals r input terminals of the first and second flip-flops. It is possible to prevent the selection from being influenced by noise, etc. by not allowing the selection to be changed.

A third aspect of the present invention is the first aspect, in which a plurality of stages of shift registers are provided on the data input terminal sides of the first and second flip-flops respectively, and the shift registers are driven by the input signal as many times as the number of stages. One clock signal can be selected from the four clock signals only when the latched results are the same and the input permission means similar to that in claim 3 permits the selection. Therefore, after selecting one clock signal, the input permission means is used to prevent the selected clock signal from being damaged due to the noise of the input signal immediately before the protection, thereby providing a large degree of margin. be able to.

(Example〕 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the bit phase synchronization circuit of the present invention, and FIG. 2 is a timing chart showing its operation.

The four clock signals CLK, , CL have a period of 2 degrees, and CLK3 and CLK4 have the same period and phases shifted by a certain period, and the occupation rate of these clock signals CLK, ~CLK is approximately 0.5. It is supplied from a clock generator (not shown). flip-flop 1 and 2
are respectively connected to the data input terminals with the clock signal CLK,
.

CLK2 is input, and when the input signal D in containing timing information is input to the clock terminal C, the input clock signals CLK, CL
2 is latched, and the latched data 11. +2 is sent to selector 3 and selector 9, respectively. The selector 3 receives four clock signals CLK, -CLK, and one of them corresponds to the combination of levels of data 11 and 12 input from flip-flops 1 and 2 shown in Table 1 below. clock signals are selected and output as a clock (3-q+3).

The flip-flop 4 receives the input signal D in at its data input terminal, latches it at the rising edge of the clock signal 13 input at the clock terminal C, and outputs data 14 . The four delay circuits 5, 6, 7.8 each input data 14, and each receives a clock signal CLK, , CLK2CLK3. CL K 4, a delay time τ1. corresponding to the phase difference between its own corresponding clock signal and a clock (not shown) being used in the receiving device at that time. τ2. τ3. τ4 is set, and the input data 14 is delayed. The selector 9 receives delay data DL output from each of the delay circuits 5 to 8.
, ~DL4 are input, and one delay data corresponding to the level combination of the input data 11 and data 12 shown in Table 1 is selected from among these, similarly to the selector 3, and the output signal is output. Output as ut. In this embodiment, it is assumed that the clock signal CL is in phase with the clock of the receiving device.

Next, the operation of this embodiment will be explained using a timing chart.

When the time L0 person input outside D in rises from the level "L" (hereinafter simply referred to as "shi") to the level "H" (hereinafter simply referred to as "H"), the clock signal CLK at that point , and CLK are all "H", so flip-flops 1 and 2 both latch the "H" state and data II.

Outputs 12. Therefore, the selector 3 selects the clock signal CLK corresponding to the combination of data 11 and 12 of "H" from Table 1, and outputs the clock signal 13 of "L" at this point.On the other hand, the input signal D in is I time L
0 to flip-flop 4, and time 1. As a result,
The clock signal 13 changes to “H” and the flip-flop 4
latches the input signal at that time (“H”) and
This data I4 is branched into four branches and sent to delay circuits 5, 6, 7, and 8, respectively, and is delayed by delay time τ1.τ2.τ3.τ4 to form delayed data D Ll , D L7 , D L3 , and D L4 are input to the selector 9. Similarly to the selector 3, the selector 9 selects data 11 or "H" according to the selection conditions shown in Table 1.
, the data 12 is "°H", so at a time 4 later than the time flllt+, the delay data DL4 from the delay circuit 8 is selected, and from then on, the output signal synchronized with the clock signal CLK is selected. the law of nature. Output as ut. According to the rise time of the input signal D in, the above-mentioned "H" from Table 1
Even if 1 to CLK3 are selected for another clock number 8C by a combination other than "-"H," the clock signal CLK, that is, the output signal D Out synchronized with the clock on the receiving side, is set at time t. , it is easy to understand that the clock signal CL in Table 1 can be extracted from
The correspondence between the combinations of K, ~CLK4 and data II and 12 is that the level or "L" is reached when the input signal D in rises, and a clock signal that can surely obtain the next rise as soon as possible is selected. .

FIG. 3 is a circuit diagram showing the configuration of a second embodiment of the present invention.

This embodiment uses flip-flops 1 and 2 of the first embodiment.
Anchor clock 3 is connected to the input terminal of clock terminal C of
1 and ant gate 32, an input signal D in is inputted to one of the two inputs, and a setting permission signal 33 is inputted to the other from a setting permission signal circuit (not shown), and a logical product is performed. It will be done. All other configurations are the same as those in the first embodiment, so explanations will be omitted. Therefore, when the setting permission signal 33 is set to "H", the flip-flop 1.2 can latch 2 to the clock signal CL at the rising point of the input signal Din, and the first The clock signal CLKI- is generated by the same operation as in the embodiment.
CLK4 is selected, but when the setting permission signal 33 is set to "Yes", it becomes impossible to newly latch with the input signal D in, and the current clock signal 1
Continue to hold 3. For example, if you first set the setting permission signal 33 to "H" to select one clock signal 13 using the method described above, and then set it to "L", from then on the input signal D in will be free from noise etc. Even if the rising point changes due to the influence, it can be made so that it does not affect the selected clock I8 No. 13.

FIG. 4 is a circuit diagram showing the configuration of a third embodiment of the present invention.

This embodiment uses flip-flops 1 and 2 of the first embodiment.
A three-stage shift register 43,44 is provided on the input side of each data input terminal, and a flip-flop 1 is provided.
3-input AND gates 41 and 42 are installed at the input ends of clock terminals C and 2, respectively. Each shift register 43, 44 has three flip-flops 451, 45, 453, . and flip-flops 46+, 46°, and 463 are connected in series, and each flip-flop 45. The input signal D in is input to the clock terminal C of 456, and the output of each stage is input to the exclusive NOR game 1-47.48. Two 3-input AND gates 41 and 42 receive an input signal D in and a setting permission signal 33 similar to the second embodiment.
and the outputs of exclusive NOR gates 47 and 48, respectively. All other configurations are the same as those in the first embodiment, so explanations will be omitted. Therefore, when an input signal is input, each shift register 43 and 44 respectively
When the input signal D in rises three times, that is, changes from "L" to "H", the latched clock signal CL
K or CLK are shifted in order and input to flip-flop 1 or 2.

Flip-flop45. If the three outputs of -453 or the three outputs of flip-flops 46 to 463 do not match, the output of exclusive NOR gate 47 or 48 becomes "L", and the inputs of AND gates 41 and 42 also become "L". “Shi”. Therefore, input 4a “F
D in can no longer be input to the clock input terminals C of flip-flops l and 2, and the flip-flop 451
or 46. The output of cannot be latched by flip-flop 1 or 2. In other words, the results of latching the input signal D in three times are the same, and the setting permission signal 33h1 is "H".
”, the clock signal CLK occurs at the rising point of the input signal D in.

CLK, can be latched by flip-flop 1.2,
One clock signal No. 9 can be selected from the four clock signals CLK and -CLK4.

This embodiment, like the second embodiment described above, first selects one clock signal 13, and then selects the setting permission signal 33.
By setting the input signal D i to “L”, the input signal D i
Although n does not have the influence of noise, etc., the rising point of the input signal D in fluctuates due to noise etc. immediately before setting the setting permission signal 33 to "L", and therefore a clock signal 13 that is not optimal is selected. This prevents the input signal from being damaged by noise, etc. Even if the rising point of is varied, the selector 3 cannot be controlled unless the same variation level is reached three times in a row. Therefore, it is possible to have a large degree of margin against temporary fluctuations in the input signal D in when selecting a clock signal. As the number of stages of the shift register increases, the margin for fluctuation increases.

(Effects of the Invention) As explained above, the present invention inputs four clock signals to the first selector, and on the other hand, when an input signal arrives, two of the four clock signals are input to the first selector. The clock signal is latched by the first and second flip-flops, and the first selector selects one clock signal from among the four clock signals based on the combination of their output levels. The latched input signal is latched and regenerated, and the latched input signal is split into four branches, each of which has a delay time corresponding to the four clock times to adjust the phase to the receiving device's clock in advance. By passing the input signal through the given four delay circuits and using the second selector to select the one that corresponds to the combination of output levels at that time, no matter what phase the input signal is input, the Since an appropriate lock signal corresponding to the phase is selected and data synchronized with the clock on the receiving device side is output, it is possible to provide a bit phase synchronization circuit that is simple to configure and requires only a short time to stabilize. , claim 2
By providing input signal input permission means at the input terminals of the clock terminals of the first and second flip-flops, the previously set clock signal is protected from JJ99 noise etc. of the subsequent input signal. According to claim 3, by using a multi-stage shift register and an input permission means provided on the first and second data input terminal sides, the temporal fluctuation of the input signal at the time of clock signal selection is suppressed. This has the effect of preventing erroneous selection of a clock signal and protecting the selected clock signal from subsequent noise.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the bit phase synchronization circuit of the present invention, FIG. 2 is a timing chart showing its operation, and FIGS. FIG. 5 is a circuit diagram showing a conventional example of a bit phase synchronization circuit, and FIG. 6 is an explanatory diagram of data acquisition with respect to clock signal CLK0 in the conventional example of FIG. 1.2.4...Flip-flop, 3.9-...Selector, 5.6, 7.8-...Delay circuit, τ1. τ2. τ3. τ4...Delay time, D Ll,
D7. D L3, D L4...delayed data D1...input signal, Dout...output signal, :+1.32.41.42-...and gate,
33...... Setting permission signal, 43, 44...
- Shift register, 47, 48--Exclusive NOR gate.

Claims (1)

[Claims] 1. A bit phase synchronization circuit that synchronizes the bits of an input signal on the receiving side of a synchronous signal transmission circuit, which has an occupancy rate of 50%.
and means for supplying four clock signals whose synchronization is equal and whose phases are sequentially shifted by 1/4 period, and two clocks whose phases are shifted by 1/4 period among the four clock signals. A signal is input to each data input terminal, and an input signal having timing information is input to each clock terminal, and the input clock signal is latched when the signal level of the input signal rises or falls. 1 and 2nd flip-flops, 4 clock signals, and 4 states based on combinations of high and low levels of the latched 2 clock signals output from the 1st and 2nd flip-flops. vs 1
a first selector that selects a corresponding clock signal from among four input clock signals according to a combination of output levels of the two flip-flops; Inputting the clock signal output from the first selector into the input terminal and inputting the clock signal output from the first selector into the clock terminal,
A third flip-flop latches the input signal when the clock signal rises or falls, and the output of the third flip-flop is branched into four and inputted to each of the four clock signals. 4 delay circuits that delay the input output of the third flip-flop by the phase difference between each corresponding clock signal and the clock on the receiving side; , a one-to-one correspondence is set between the four states based on the combination of high and low levels of the two clock signals output from the first and second flip-flops, and the combination of the output levels of the two flip-flops , the corresponding one from among the outputs of the four input delay circuits.
and a second selector for selecting one output. 2. The device according to claim 1, further comprising means for permitting input of the input signal to the clock terminal only when a setting permission signal is input from the outside to the input side of the clock terminal of the first and second flip-flops. bit phase synchronization circuit. 3. Installed on the data input terminal side of each of the first and second flip-flops, and receiving two clock signals whose phases are shifted by 1/4 period out of the four clock signals to the data input terminals. a multi-stage shift register that latches and shifts the input clock signal each time the input signal input to the clock terminal rises or falls; and inputs to the clock terminals of each of the first and second flip-flops. from the multi-stage shift register to the first or second flip-flop only when the outputs of each stage of the multi-stage shift register match each other and are permitted by the setting permission signal. Claim 1 further comprising means for latching the input of
The described bit phase synchronized circuit.