JPH0277802A - Digital signal processing circuit - Google Patents
Digital signal processing circuitInfo
- Publication number
- JPH0277802A JPH0277802A JP22839288A JP22839288A JPH0277802A JP H0277802 A JPH0277802 A JP H0277802A JP 22839288 A JP22839288 A JP 22839288A JP 22839288 A JP22839288 A JP 22839288A JP H0277802 A JPH0277802 A JP H0277802A
- Authority
- JP
- Japan
- Prior art keywords
- processing
- message
- dsp
- interruption
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000004891 communication Methods 0.000 claims abstract description 11
- 238000004886 process control Methods 0.000 abstract description 6
- 235000019800 disodium phosphate Nutrition 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ディジタル数値化された信号を論理処理も
しくは演算処理することによって所望の機能を実現でき
るディジタル信号処理回路(以下DSPという)に関す
るものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital signal processing circuit (hereinafter referred to as DSP) that can realize a desired function by performing logical processing or arithmetic processing on digitalized signals. It is.
第5図は伝送特性自動測定装置の一例を示す構成図であ
る。この図において、21はマイクロコンピュータ、2
2は測定トーン発生用DSP、23はモデモ信号変調用
DSP、24はレヘルメータ用DSP、25はモデモ復
調用DSP、26はゲート、27はD/A変換器、28
はA/D変換器、29はスムージング用ローパスフィル
タ、30はサンプル・ホールド回路、31はノイズ除去
用ローパスフィルタ、32は平衡出力用トランス、33
は平衡/不平衡トランスである。FIG. 5 is a configuration diagram showing an example of an automatic transmission characteristic measuring device. In this figure, 21 is a microcomputer;
2 is a DSP for generating a measurement tone, 23 is a DSP for modemo signal modulation, 24 is a DSP for a level meter, 25 is a DSP for modemo demodulation, 26 is a gate, 27 is a D/A converter, 28
is an A/D converter, 29 is a smoothing low-pass filter, 30 is a sample/hold circuit, 31 is a noise removal low-pass filter, 32 is a balanced output transformer, 33
is a balanced/unbalanced transformer.
このように構成された伝送特性自動測定装置では、各機
能の起動、停止がマイクロコンピュータ21よりI10
バスを介して行われ、例えば測定トーンを発生させるた
めにはオシレータの機能を具現化するプログラムを内蔵
した測定トーン発生用DSP22のみに起動コマンドが
与えられる。In the automatic transmission characteristic measuring device configured in this way, starting and stopping of each function is controlled by the microcomputer 21 via I10.
For example, in order to generate a measurement tone, an activation command is given only to the measurement tone generation DSP 22, which has a built-in program that embodies the function of an oscillator.
しかし、上記のように従来は、1個のDSPにつき1つ
の機能しか具現化していなかったため、複数個のDSP
が必要となっており、コストを増大させていた。However, as mentioned above, in the past, only one function was implemented per DSP, so multiple DSPs
is required, increasing costs.
この発明は、上記の課題を解決するためになされたもの
で、1個で同時に複数の機能を具現化できるDSPを得
ることを目的とする。The present invention was made to solve the above-mentioned problems, and aims to obtain a DSP that can simultaneously implement a plurality of functions with a single DSP.
この発明に係るDSPは、制御用コンピュータとの通信
手段と、各処理機能を選択的に起動、停止する起動手段
および停止手段と、割り込み源に対して処理機能を対応
させる複数の準備手段と、処理を行う複数の処理手段と
、処理を停止させるとともに割り込みを不許可にする複
数の終結手段と、割り込み源に対して割り当てられた処
理機能を選択的に実行させる実行制御手段と、複数の処
理機能の準備手段、IA埋千手段終結手段を時分割で連
続的に、または1つの処理機能の準備手段。The DSP according to the present invention includes a means for communicating with a control computer, a starting means and a stopping means for selectively starting and stopping each processing function, and a plurality of preparation means for making processing functions correspond to interrupt sources. A plurality of processing means for performing processing, a plurality of termination means for stopping processing and disabling interrupts, an execution control means for selectively executing a processing function assigned to an interrupt source, and a plurality of processing means. Preparing means for functions, means for terminating IA filling means continuously in a time-sharing manner, or preparing means for one processing function.
処理手段、終結手段を連続的に実行させるプロセス制御
手段とを備えたものである。It is equipped with a process control means for continuously executing processing means and termination means.
この発明においては、各処理機能を具現化するプロセス
を時分割で制御することにより複数の処理機能が同時に
実行されることになる。In this invention, a plurality of processing functions are executed simultaneously by controlling the processes that implement each processing function in a time-sharing manner.
〔実施例)
第1図はこの発明のDSPの一実施例の構成を示す図で
ある。この図において、1は図示しない制御用コンピュ
ータとの通信手段、1aはメツセージ手段、2.3は各
処理機能を選択的に起動。[Embodiment] FIG. 1 is a diagram showing the configuration of an embodiment of a DSP of the present invention. In this figure, 1 is a communication means with a control computer (not shown), 1a is a message means, and 2.3 is a means for selectively activating each processing function.
停止する起動手段および停止手段、4は割り込み源に対
して処理機能を対応させる準備手段、5は論理手段、演
算処理等の処理を行う処理手段、6は処理の実行を停止
するとともに割り込みを不許可にする終結手段、7は割
り込み源に対して割り当てられた処理機能を選択的に実
行する実行制御手段、8はプロセス制御手段で、複数の
処理機能の準備手段4.処理手段5.終結手段6を時分
割で連続的に、または1つの処理機能の準備手段411
L理手段5.終結手段6を連続的に実行させる。9はゲ
ート、10はこの発明のDSPを示す。また、第2図は
処理機能の具現化を示すタイムチャートを示す図であり
、第3図、第4図はそれぞれI10バス、2ボ一トRA
M11を用い、この発明のDSPloを接続した例を示
す図である。4 is a preparation means for making a processing function correspond to an interrupt source; 5 is a logic means; a processing means for processing such as arithmetic processing; 6 is a means for stopping execution of processing and disabling interrupts; 7 is an execution control means for selectively executing the processing function assigned to the interrupt source; 8 is a process control means; means for preparing a plurality of processing functions; 4. Processing means 5. The finishing means 6 can be performed continuously in a time-sharing manner, or the preparation means 411 for one processing function.
L-method 5. The termination means 6 are executed continuously. 9 represents a gate, and 10 represents a DSP of the present invention. Further, FIG. 2 is a diagram showing a time chart showing the implementation of processing functions, and FIGS. 3 and 4 are diagrams showing I10 bus, 2-bot RA
FIG. 3 is a diagram showing an example in which DSPro of the present invention is connected using M11.
次に動作について説明する。Next, the operation will be explained.
まず、制御用のマイクロコンピュータ21から通信手段
1を介して送出される起動メツセージを受けると、起動
手段2により特定の処理機能が選択的に起動される。す
なわち、この時、準備手段4により割り込み源に対して
の処理機能の対応付けが行われるとともに、割り込み許
可および実行許可が指示される。次いで割り込みがある
と、プロセス制御手段8によりこの割り込みに対応した
制御プロセスが選択され、処理手段5により処理が行わ
れる。そして、メツセージを送出する必要がある場合に
は、メツセージ手段1aから通信手段1を介してマイク
ロコンピュータ21へのメツセージの送出が行われる。First, upon receiving an activation message sent from the control microcomputer 21 via the communication means 1, the activation means 2 selectively activates a specific processing function. That is, at this time, the preparation means 4 associates the processing function with the interrupt source, and instructs interrupt permission and execution permission. Next, when an interrupt occurs, the process control means 8 selects a control process corresponding to this interrupt, and the processing means 5 performs processing. When it is necessary to send a message, the message is sent from the message means 1a to the microcomputer 21 via the communication means 1.
以後、同様に割り込みに対して処理が行われ、処理手段
5により自立的に停止信号が送出されるかマイクロコン
ピュータ21から停止メツセージが送出されると、停止
手段3により終結手段6が起動され、割り込み不許可お
よび実行不許可が指示される。Thereafter, the interrupt is processed in the same way, and when the processing means 5 autonomously sends out a stop signal or the microcomputer 21 sends out a stop message, the stopping means 3 activates the terminating means 6, Instructs to disable interrupts and disable execution.
この際、通常は終結前に通信手段1を介してマイクロコ
ンピュータ21との通信が行われるが、プロセスが自立
的に停止する場合には通信は行われない。また、他の割
り込み源に対する処理機能についても同様の手順で具現
化される。At this time, communication with the microcomputer 21 is normally performed via the communication means 1 before termination, but if the process is stopped autonomously, no communication is performed. Furthermore, processing functions for other interrupt sources are also implemented using similar procedures.
すなわち、この発明のDSPloでは各処理機能を具現
化するプロセスを時分割で制御することにより複数の処
理機能を同時に実現することが可能になり、他の処理機
能に影響を及ぼすことなく指定された処理機能を実現で
きる。In other words, the DSPLo of this invention makes it possible to realize multiple processing functions at the same time by controlling the processes that embody each processing function in a time-sharing manner. Processing functions can be realized.
したがって、第3図または第4図に示すように接続すれ
ば、1個のDSPIOを用いるだけで第5図に示したも
のと等価な伝送特性自動測定装置を実現することができ
、装置の低コスト化が図れなお、第1図に示したこの発
明のDSPloを構成する各手段は、実際にハードで構
成しても相当の効果があるが、通常市販されている汎用
のDSPを用い各構成要求をソフトウェアで構成すれば
容易に実現でき、この場合、本体の小型化が可能になり
一層機能的となる。Therefore, by connecting as shown in Fig. 3 or 4, it is possible to realize a transmission characteristic automatic measurement device equivalent to that shown in Fig. 5 by using only one DSPIO, and the device has a low cost. In addition, each means constituting the DSPLo of the present invention shown in FIG. 1 can be considerably effective even if it is actually constructed by hardware, but it is not possible to reduce the cost by using a commercially available general-purpose DSP. The requirements can be easily realized by configuring them in software, and in this case, the main body can be made smaller and more functional.
また、この発明のDSPloは上記の伝送特性自動測定
装置に限らず、テレコミュニケーション、ロボット、画
像処理機能等のあらゆる分野に応用可能であることはい
うまでもない。Furthermore, it goes without saying that the DSPLo of the present invention can be applied not only to the automatic transmission characteristic measuring device described above, but also to all fields such as telecommunications, robots, and image processing functions.
この発明は以上説明したとおり、制御用コンピュータと
の通信手段と各処理機能を選択的に起動、停止する起動
手段および停止手段と、割り込み源に対して処理機能を
対応させる複数の準備手段と、処理を行う複数の処理手
段と、処理を停止させるとともに割り込みを不許可にす
る複数の終結手段と、割り込み源に対して割り当てられ
た処理機能を選択的に実行させる実行制御手段と、複数
の処理機能の準備手段、処理手段、終結手段を時分割で
連続的に、または1つの処理機能の準備手段、処理手段
、終結手段を連続的に実行させるプロセス制御手段とを
備えたので、各処理機能を具現化するプロセスを時分割
で制御することにより複数の処理機能が同時に実行でき
、1個のDSPで複数の処理機能を同時に具現化できる
という効果がある。As described above, the present invention includes a communication means with a control computer, a starting means and a stopping means for selectively starting and stopping each processing function, and a plurality of preparation means for making processing functions correspond to interrupt sources. A plurality of processing means for performing processing, a plurality of termination means for stopping processing and disabling interrupts, an execution control means for selectively executing a processing function assigned to an interrupt source, and a plurality of processing means. Each processing function is equipped with a process control means that continuously executes the preparation means, processing means, and termination means of a function in a time-sharing manner, or continuously executes the preparation means, processing means, and termination means of one processing function. By time-sharingly controlling the process that implements the process, multiple processing functions can be executed simultaneously, and one DSP can implement multiple processing functions at the same time.
第1図はこの発明のDSPの一実施例の構成を示す図、
第2図は処理機能の具現化を示すタイムチャート、第3
図、第4図はこの発明のDSPの接続例を示す図、第5
図は伝送特定自動測定装置の従来例を示す構成図である
。
図中、1は通信手段、1aはメツセージ手段、2は起動
手段、3は停止手段、4は準備手段、5は処理手段、6
は終結手段、7は実行制御手段、8はプロセス制御手段
、9はゲート、10はこの発明のDSP、+1は2ボー
1−RAMである。FIG. 1 is a diagram showing the configuration of an embodiment of the DSP of the present invention,
Figure 2 is a time chart showing the implementation of processing functions;
Figures 4 and 5 are diagrams showing connection examples of the DSP of the present invention.
The figure is a configuration diagram showing a conventional example of a transmission specific automatic measuring device. In the figure, 1 is a communication means, 1a is a message means, 2 is a starting means, 3 is a stopping means, 4 is a preparation means, 5 is a processing means, 6
7 is a termination means, 7 is an execution control means, 8 is a process control means, 9 is a gate, 10 is a DSP of the present invention, and +1 is a 2-baud 1-RAM.
Claims (1)
処理回路であって、前記制御用コンピュータとの通信手
段と各処理機能を選択的に起動、停止する起動手段およ
び停止手段と、割り込み源に対して処理機能を対応させ
る複数の準備手段と、処理を行う複数の処理手段と、処
理を停止させるとともに割り込みを不許可にする複数の
終結手段と、割り込み源に対して割り当てられた処理機
能を選択的に実行させる実行制御手段と、前記複数の処
理機能の前記準備手段、処理手段、終結手段を時分割で
連続的に、または1つの処理機能の前記準備手段、処理
手段、終結手段を連続的に実行させるプロセス制御手段
とを備えたことを特徴とするディジタル信号処理回路。A digital signal processing circuit controlled by a control computer, comprising a communication means with the control computer, a starting means and a stopping means for selectively starting and stopping each processing function, and a processing function for an interrupt source. A plurality of preparation means to correspond, a plurality of processing means to carry out processing, a plurality of termination means to stop processing and disable interrupts, and to selectively execute processing functions assigned to interrupt sources. A process in which an execution control means and the preparation means, processing means, and termination means of the plurality of processing functions are executed continuously in a time-sharing manner, or the preparation means, processing means, and termination means of one processing function are executed continuously. A digital signal processing circuit comprising a control means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63228392A JPH0820888B2 (en) | 1988-09-14 | 1988-09-14 | Digital signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63228392A JPH0820888B2 (en) | 1988-09-14 | 1988-09-14 | Digital signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0277802A true JPH0277802A (en) | 1990-03-16 |
| JPH0820888B2 JPH0820888B2 (en) | 1996-03-04 |
Family
ID=16875749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63228392A Expired - Fee Related JPH0820888B2 (en) | 1988-09-14 | 1988-09-14 | Digital signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0820888B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03283976A (en) * | 1990-03-30 | 1991-12-13 | Toshiba Corp | Picture reproducing device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653915A (en) * | 1979-10-08 | 1981-05-13 | Nissan Diesel Motor Co Ltd | Cooler for automobile |
| JPS60194817A (en) * | 1984-03-16 | 1985-10-03 | Sony Corp | Digital signal processor |
| JPS63102492A (en) * | 1986-10-17 | 1988-05-07 | Fujitsu Ltd | Digital signal processor |
-
1988
- 1988-09-14 JP JP63228392A patent/JPH0820888B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653915A (en) * | 1979-10-08 | 1981-05-13 | Nissan Diesel Motor Co Ltd | Cooler for automobile |
| JPS60194817A (en) * | 1984-03-16 | 1985-10-03 | Sony Corp | Digital signal processor |
| JPS63102492A (en) * | 1986-10-17 | 1988-05-07 | Fujitsu Ltd | Digital signal processor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03283976A (en) * | 1990-03-30 | 1991-12-13 | Toshiba Corp | Picture reproducing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0820888B2 (en) | 1996-03-04 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |