JPH0278227A - Collector-isolated diffused transistor and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a collector-isolated diffused transistor and a manufacturing method thereof.

[Conventional technology]

FIG. 2 is a cross-sectional view showing an example of a conventional method for manufacturing a collector-isolated diffused transistor.

First, as shown in FIG. 2(a), a P-type silicon substrate 1
A collector region 22 is formed by introducing impurities into the +n'' type buried layer.

Next, as shown in FIG. 2(b), a P-type silicon substrate 1
After several high resistivity p-type epitaxial layers 21 are grown thereon, an n0 isolation diffusion region 32 is formed.

Subsequently, as shown in FIG. 2(c), after a shallow p-type impurity 23 is diffused throughout the P-type silicon substrate 1, n0
An emitter region 24 is formed. At this time, the p-type impurity 23 diffuses inward and has a gradient distribution as shown by the broken line 23' in the figure.

Finally, as shown in FIG. 2(d), a contact hole is formed in the glabella insulating film 31, and a collector electrode 42, a pace electrode 43, and an emitter electrode 44 are formed to form a transistor.

The transistor formed in this way.

(2) Since the high-resistivity p-type epitaxial layer 21 grown on the p-type silicon substrate 1 is relatively thin, the n9 isolation diffusion region 32 is formed with less lateral spread and the device area can be reduced.

■ Due to the high impurity concentration in the collector, the accumulated charge under forward bias is reduced and the switching speed is increased.

■ High hfe at low and high currents.

There are advantages such as

[Problem to be solved by the invention]

However, to create the above-mentioned transistor, it is essential to grow an epitaxial layer during the process. Therefore, there is a drawback that the cost required for epitaxial growth is high.

An object of the present invention is to provide a collector-isolated diffusion transistor having the same performance as the above-described transistor without using epitaxial growth, and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, the collector-isolated diffused transistor of the present invention includes a transistor consisting of an emitter region/base region and a collector region formed on a silicon substrate, and a dug layer formed directly under the collector region. It has the following.

In the method for manufacturing a collector-isolated diffused transistor of the present invention, there is a step of forming a transistor consisting of an emitter region, a base region, and a collector region on a silicon substrate, and the side surface is perpendicular to the surface of the silicon substrate immediately below the collector region. The method includes a step of forming a dug layer, a step of introducing impurities into the dug layer by ion implantation, and a step of removing a part of silicon inside the dug layer.

[Effect]

A base region, an emitter region, and an isolation diffusion region are formed on one side of the silicon substrate, while a dug layer is formed on the back side of the silicon substrate, and impurities are introduced into the dug layer by ion implantation to form a collector region. form. The transistor produced in this manner can be similar to the conventional method without using epitaxial growth, and the cost can be reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

In FIG. 1(a), first, for example, phosphorus is introduced as an impurity into a high resistivity P-type silicon substrate 11 (hereinafter referred to as a P-silicon substrate) to form an n0 isolation diffusion region 32.

Next, as shown in FIG. 1(b), a P-silicon substrate 1
After shallow p-type impurity is diffused throughout the n0 emitter region 24, the n0 emitter region 24 is formed. At this time, p-type impurity region 2
3 diffuses inward and has a slope distribution as shown by the broken line 23' in the figure.

Next, as shown in FIG. 1(c), after forming a glabellar insulating film 31 and a mask oxide film 31', a mask oxide film 31' is formed using ordinary photolithography and etching.
Pattern formation is performed.

Subsequently, as shown in FIG. 1(d), a mask oxide film 3 is formed.
1' as a mask, a dug layer 12 having side surfaces perpendicular to the surface of the P-silicon substrate 11 is formed in contact with the isolation diffusion region by, for example, sputter etching. Then, impurities are introduced by ion implantation to form a collector region 22'. At this time, a small amount of impurity due to the ion implantation is also introduced into the side surface of the dug layer 12 due to variations in the ion implantation angle.

Therefore, after ion implantation, for example, using a nitric-fluoric acid aqueous solution (for example, HF:HNO, :H20=1:1:2),
The silicon inside the dug layer 12 is etched to the extent that impurities that have entered the side surfaces can be removed.

Subsequently, as shown in FIG. 1(e), an interlayer insulating film 31 is formed.
A contact hole is formed in the wafer, and a five collector electrode 42, a base electrode 43, and an emitter electrode 44 are formed to form a transistor.

With such a structure, a transistor having the same characteristics as conventional transistors can be obtained without using an epitaxial layer. Therefore, there is no need to grow an epitaxial layer, and costs can be reduced. What is required instead of the epitaxial growth process is the process of forming a dug layer and the process of etching the silicon inside the dug layer, but these processes are common processes and are does not complicate the process.

In addition, in forming the dug portions, if the area of the dug portions is made somewhat larger, slight misalignment will not be a problem, and due to the structure of the present invention, the yield of the device will be reduced. Very rarely.

Further, the present invention can also be applied to a bipolar transistor as shown in FIG. That is, an emitter region 24, a base region 26, a collector contact region 25, and an emitter electrode 44 which is a metal electrode are formed in an area surrounded by an insulating separation layer 33 in an n-type epitaxial layer 20 grown on a P-type silicon substrate 11. , the present invention can be applied to a buried diffusion layer 50 formed to reduce the electrical resistance of the collector in a transistor constituted by a base electrode 43 and a collector electrode 42. In this case, the buried diffusion layer 50 is formed by forming a dug layer in the region immediately below the buried diffusion layer 50 and then introducing impurities by using ion implantation, in the same manner as in the step of FIG. 1(d). It can be achieved. In this case, the collector region 27 must be made n-type by diffusion.

〔Effect of the invention〕

As described above in detail, according to the present invention, a transistor having the same characteristics as conventional transistors can be obtained without using an epitaxial layer. Therefore, the process of growing an epitaxial layer is eliminated, and costs can be reduced.6 The processes necessary to achieve the present invention are those commonly used to create silicon devices, so the process is simple. It does not add complexity or reduce yield.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the structure of each step of an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views showing an example of a conventional collector-isolated diffusion transistor. , FIG. 3 is a sectional view showing an example of application of the transistor of the present invention. DESCRIPTION OF SYMBOLS 11...P-silicon substrate 12...Engraving layer 20...N-type epitaxial layer 21...High resistivity p-type epitaxial layer 22.22'
...n0 collector region 23...P type impurity region 2
3'...Gradient distribution of P-type impurity region 24...n''''
``Emitter region...Collector contact region 26...Base region 27...Collector region 31...Interlayer insulating film 31'...Mask oxide film 32...Isolation diffusion region 33...Insulating isolation layer 42...Collector electrode 43...Base electrode 44...Emitter electrode

Claims (2)

[Claims] (1) A collector isolation diffusion transistor characterized by having a transistor consisting of an emitter region, a base region, and a collector region formed on a silicon substrate, and a dug layer formed directly under the collector region. (2) a step of forming a transistor including an emitter region, a base region, and a collector region on a silicon substrate, and a step of forming a dug layer whose side surfaces are perpendicular to the surface of the silicon substrate directly below the collector region; A method for manufacturing a collector-isolated diffused transistor, comprising the steps of introducing impurities into the dug layer by ion implantation, and removing a portion of silicon inside the dug layer.