JPS6065543A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a manufacturing method and structure of a semiconductor device.
The present invention relates to a method of implanting impurities into the lower portions of all trenches and removing or compensating for unnecessary p-type impurity regions in a subsequent silicon etching step or NG region formation step.

[Background of the invention]

In the semiconductor device previously disclosed in Japanese Patent Application No. 56-177201, etc., when implanting p-type impurities to be provided below the trench for element isolation, as shown in FIG. This was done by covering it with a For example, in the structure in which the IJ near element and the I"L element coexist as shown in FIG. A p-type impurity p is implanted in the wafer, which requires an extra photoresist process.

In Fig. 1, 1 is a p(n) type Si substrate, 2 is an n+
(p+) buried layer, 3 an n(p) type SiZ epitaxial growth layer, 100 an insulating film, 400 a photoresist), and 4a a p(n) type diffusion layer.

[Purpose of the invention]

The purpose of the present invention is to eliminate the photoresist process required in the above-mentioned conventional method, form p-type impurities also under the grooves of the I"L, and use the sickle process to remove unnecessary parts other than the separation part of the linear part. Nap
The object of the present invention is to provide a method for obtaining a structure having the same function as that obtained by using a photoresist process by removing the Ij1 impurity.

[Summary of the invention]

For the above purpose, in the present invention, when etching the island of the LI"L part I where the n-type impurity P is implanted under all the grooves, the bow groove part of the I2L part is also etched at the same time,
Unnecessary n-type impurities in areas other than the element isolation region in the linear portion are removed. Alternatively, a step of implanting an n-type impurity n to compensate for the unnecessary n-type impurity region may also be used.

[Embodiments of the invention]

The present invention will be explained in detail below. First of all, FIG. 2 shows the first embodiment of the present invention, in which unnecessary P is removed in the etching process of the I"L part
FIG. 4 is a cross-sectional view illustrating the forming process in order of process when removing the mold region 4b.

In FIG. 2(a), an n+ type region 2 is formed on a p type semiconductor substrate 1, an n type epitaxial layer 3 is laminated, an oxide film 100 thereon is photoetched, and silicon is etched using the oxide film 100 as a mask. Separation grooves 200, 201
After forming a p-type region 4a and undergoing an oxidation process, a p-type impurity p6 is injected into the entire surface to form a p-type region 4a.

FIG. 4b is a cross-sectional view when forming 4b. Next, as shown in FIG. 2(b), the oxide film 100 in the I2L portion I is removed. Next, silicon 3 is etched. After a subsequent oxidation step (FIG. 2(C)), the oxide film is removed from the entire surface and the n-type impurity is diffused, resulting in the state shown in FIG. 2(d). Finally, a p+ type region 220 and an n+ type region 10 which become a base and an emitter, respectively.
After opening the window for taking out the electrode, the result is shown in Fig. 2(e). By etching the I2L part I after FIG. 2(b), the p-type region 4b other than the isolation p-type region 4a in the linear part is removed, thereby eliminating the conventionally required isolation of the 2L part. This makes it possible to eliminate the photo process for covering the groove 201.

FIG. 3 shows a second embodiment of the present invention, and shows the formation process when an oxide film is removed from the entire surface of the hill where the n-type impurity was implanted with P in FIG. 2(a). Figure 3(a) shows the second
It is a sectional view when an oxide film is removed from the entire surface after the steps up to Figure (a) and then oxidized. Thereafter, the oxide film in the I2L portion (3) is removed by photoetching, and the silicon 3 in the (2L) portion I is etched, at which time the p-type region 4b under the isolation trench 201 is also removed at the same time. After the subsequent oxidation process, the third
After diffusion of n-type impurities, the result shown in FIG. 3(b) becomes FIG. 3(c). If the sickle, base, emitter, and contact holes are formed, a structure similar to that shown in FIG. 2(e) will be obtained.

FIG. 4 shows a third embodiment of the present invention.
This figure shows a forming process in which the type region 4b is removed and further an n-type impurity is implanted into that region. Figure 4 (
a) is a cross-sectional view when an n-type impurity n is implanted under the isolation trench 201 through a photo process after FIG. 3(b) to form an n-type region 5 having a concentration sufficient to compensate for the p-type region 4b. It is. FIG. 4(b) is a cross-sectional view of the ridge after the n-type impurity is diffused.

FIG. 5 shows the fourth embodiment of the present invention, in which the linear part is npn)
The formation process for providing the n+ type region isolation groove 200 at the bottom of the collector of the transistor is shown in accordance with the process shown in FIG. 3. FIG. 5(a) shows a cross-sectional view at the time of implantation of n-type impurities after silicon is etched to the collector portion of the npn transistor to form an isolation groove 200. The subsequent steps are performed in the same manner as in FIG. 3, resulting in FIGS. 5(b), (C), (d), and (e). As shown in FIG. 5(e), there is a p-type region 4a around the n+-type region 11 forming the collector terminal of the npn transistor, but the n+-type region 11 is in contact with the n+-type region 2. There is no problem at all as long as such a structure is used.

In addition, even if 11 and 2 are formed slightly apart due to manufacturing variations and some p-region 4a is present between them, results are obtained with no particular problem in device characteristics.

According to this structure, an element with low collector resistance can be obtained without performing a deep n+ expansion for the collector terminal.

FIG. 6 shows a fifth embodiment of the present invention, in which an n-type impurity as shown in FIG. This figure shows the formation process when implants are used together. Figure 6 (a
), the silicon etching of the I”L portion I,
After the oxidation, an n-type impurity n is implanted in the separation groove 201 of the I'L part 2 and the part where the collector slip-type head region 11 of the npn transistor is to be formed by a photo process to compensate for the n-type region in the said part. It is. After that, the state becomes as shown in FIGS. 6(b) and 6(C).

By this method, in FIG. 5(e), the left side of the n+ type region 11,
That is, unnecessary n-type region 4b on the active region side can be removed.

〔Effect of the invention〕

According to the present invention, the separation groove for forming the confectionery separation region and the n-type region for junction separation below the groove can be formed by only one photoresist process for determining the separation groove. That is, by etching the silicon in the I2L portion of the sickle to remove the p-type region under the isolation groove, which is necessary for the silicon, the photoresist process can be omitted, and the effect of reducing the number of processes is significant.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of ion implantation performed by covering areas other than the desired area with resist using the conventional method, and Figure 2 (a)
) to (e) are cross-sectional views showing the manufacturing process of the first embodiment of the present invention in order of process, and FIGS. 3(a) to (C) are cross-sectional views of the second embodiment of the present invention.
4(a) and (b) are cross-sectional views showing the manufacturing process of the third embodiment of the present invention in order of process, and FIGS. (e) is a sectional view showing the manufacturing process of the fourth embodiment of the present invention in order of process;
Figures (a) to (e) are cross-sectional views showing the manufacturing process of the fourth embodiment of the present invention in order of process. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n+ type region 3...n-type epitaxial layer, 4a, 4b...n-type region, 5...n-type region (compensation part of n-type region for junction isolation), 100.101,10
2... Oxide film, 200, 201... Separation groove, 300... Step difference between linear part and I"L part, 400... Photoresist), 10.1
1...n+ type territory 20...p+ type territory 7th day 2nd mouth 2nd mouth 4 mouths 5th day 5th figure 6th country

Claims (1)

[Claims] 1. A second conductivity type semiconductor layer is formed on a first conductivity type semiconductor substrate, and the semiconductor layer is separated into a plurality of islands by providing a groove on the surface and a channel blocking region of the first conductivity type below the groove. When forming isolation regions, impurities for forming channel blocking regions of the first conductivity type are introduced under all of the grooves after the grooves are formed, and an etching process of the silicon using the iron or a semiconductor layer of the second conductivity type is performed. 1. A method for manufacturing a semiconductor device, comprising removing a channel blocking region of a first conductivity type at a necessary location, and compensating for impurities therein.