JPH0282294A - Data driver of matrix display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A matrix display device for applying a data voltage to a matrix display panel interposed between a data bus and a scan canvas in which display media such as liquid crystal and EL are orthogonally arranged. The purpose of this data driver is to make it applicable to both sequential sampling for black-and-white display, etc., and simultaneous sampling of R, G, and B signals for color display. In a data driver of a matrix display device that applies a data voltage to the data bus of a matrix display panel arranged orthogonally, shift data is shifted in response to a shift clock signal, and shift output signals corresponding to the data bus are sequentially output. A sample bold circuit samples display data corresponding to the data bus and outputs the data voltage, a shift output signal of the shift register and three control signals are added, and the length of the shift data is and a timing selection circuit that applies a sampling timing signal according to the timing of the three control signals and the timing of the three control signals to the sample and hold circuit.

[Industrial application field]

The present invention relates to a data driver for a matrix display device for applying a data voltage to a matrix display panel interposed between a data bus and a scan canvas in which display media such as liquid crystals and EL are orthogonally arranged. be.

Currently, small-sized liquid crystal color television receivers on the market use a matrix display panel in which a liquid crystal is sealed between a data bus and a scan canvas arranged orthogonally to each other, and a color filter is provided. Such matrix display panels are expected to have an increased display capacity and larger size, and are also being considered for application as display terminal devices for computers. Therefore, a data driver that can ensure display quality for various uses is required.

[Conventional technology]

A video signal according to the NTSC standard is, for example, a composite signal of a luminance signal, a color difference signal, and a synchronization signal, as shown in FIG. 14, and when this video signal is separated and demodulated,
For example, the synchronization signal SYN and R(
(red), G (green), and B (blue) luminance signals.

In the case of R10+B, white is displayed. Further, the video signal output from a computer etc. is for displaying characters or graphics, and usually includes a synchronizing signal SYN and R, G as shown in FIG.

B signal.

When using a matrix display panel such as a liquid crystal display panel, the scan canvas is sequentially scanned according to the synchronization signal SYN, and a data voltage obtained by sample-holding the R, G, and B signals within one scanning period is applied to the data bus. FIG. 16 shows a block diagram of the main parts of a conventional data driver for outputting a data voltage. In the figure, 81 is a sampling switch consisting of a transistor, etc., 82 is a holding capacitor, 83 is a buffer circuit, 84 is a shift register, 85 is a sample and hold circuit 86 is a level converter, 87 is an analog buffer circuit, Q1 to Q
n is an output terminal connected to one data bus of the matrix display panel, SL is shift data, CLK is a shift clock signal, OE is an enable signal, and Vll is a voltage of a power supply such as 0.

The shift register 84 sequentially shifts the shift data SI in accordance with the shift clock signal CLK, and uses the shift output signals 81 to Sn as sampling timing signals of the sample hold circuit 85 via the level converter 86, and converts the input R, G, B signals is sampled by the sampling switch 81, held by the capacitor 82, the buffer circuit 83 is simultaneously activated by the enable signal OE via the level converter 86, and the data voltage corresponding to the hold voltage of the capacitor 82 is simultaneously output for the ■ line. It is output from terminals Q1 to Qn and applied to the data bus of the matrix display panel.

FIG. 17 shows R, G, B signals and shift output signals Sl, S2 . S3. ..., and the shift output signal is sequentially sent to the sample and hold circuit 85.
Since the R, G, and B signals are sampled and held at the level at the time of the circle mark, data voltages according to the hold outputs are output, and R, G, and B color display is performed.

[Problem to be solved by the invention]

When a display device equipped with a matrix display panel such as a liquid crystal display panel or an EL display panel in which a data bus and a scan bus are orthogonally arranged is used as a display terminal device for a computer, one dot of display data is , B3
This will correspond to pixels. In that case, R in Figure 18
The display data shown in GB is displayed at times tl, t2 . The R, G, and B signals are sequentially sampled and held according to the shift output signals St, S2, and 33 at t3, and are displayed in correspondence with the three R, G, and B pixels.

However, display data I? In CB, waveform distortion occurs as shown by RGB' due to the capacitance of the transmission path, etc. Therefore, when the R signal is sampled and held at time t1 according to the shift output signal S1, the waveform distortion part Therefore, accurate sampling of display data is not possible.

In order to eliminate this drawback, it would be sufficient to provide an output section with a large current capacity that can rapidly charge and discharge the capacitance of the transmission path, but this results in the drawback of increased power consumption.

Furthermore, as shown in FIG. 19, a data driver that performs simultaneous sampling is also known. That is, the shift register 94
The three sampling switches 91 of the sample and hold circuit 95 are operated simultaneously by the shift output signal of
R, G, B (signals) are simultaneously sampled, held by a capacitor 92, and outputted to output terminals Q1, Q2, .
. . . A data voltage is applied to a data bus of a matrix display panel (not shown).

However, in the sample hold circuit 95, R, G,
It becomes possible to sample the B signal at the same time,
When applied to a matrix display panel with a small display capacity and black and white display, there is a drawback that the numbering interval becomes thick, resulting in a decrease in display resolution.

As mentioned above, the data driver of conventional matrix display devices has either a sequential sampling configuration or a simultaneous sampling configuration, and in the case of the sequential sampling configuration, the display quality deteriorates due to the influence of waveform modification. However, in the case of the simultaneous sampling configuration, a reduction in resolution becomes a problem when displaying a moving image or the like using a display panel having a configuration with a relatively small display capacity.

The present invention aims to be applicable to both sequential sampling and simultaneous sampling.

[Means to solve the problem]

The data driver of the matrix display device of the present invention has a first
To explain with reference to the figure, this is a data driver for applying a data voltage to a data bus 1 of a matrix display panel 3 in which a data bus 1 and a scan canvas 2 are orthogonally arranged, and shifts shift data according to a shift clock signal. A shift register 4 sequentially outputs shift output signals corresponding to the data bus 1, and a sample hole 4 that samples display data and outputs a data voltage corresponding to the data bus.
The shift output signal of the shift register 4 and three control signals are added to the code circuit 5, and a sampling timing signal according to the length of the shift data and the timing of the three control signals is sent to the sample hold circuit 5. The sample and hold circuit 5 is connected to the data bus l of the matrix display panel 3.
A data voltage is applied to each line via the analog buffer circuit 7, and scan pulses are sequentially applied to the scan canvas 2 of the matrix display panel 3 from the scan driver 8.

[For production]

The timing selection circuit 6 is constituted by an AND circuit or a latch circuit, and if it is constituted by an AND circuit, by making the shift data as long as 3 shift clock signals, there will be a time for the 3 shift output signals to overlap. ,
If the three control signals are applied at the same time, the timing selection circuit 6 applies a sampling timing signal to the sample hold circuit 5 for simultaneously sampling the R, G, and B signals. Furthermore, by setting the three control signals to different timings, a sampling timing signal for sequentially sampling the R, G, and B signals is applied to the sample-and-hold circuit 5.

Therefore, by selecting the timings of the three control signals, it is possible to apply both sequential sampling and simultaneous sampling.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention, and 1
1-1 to 11-n are sampling switches made of transistors, etc., 12-1 to 12-n are holding capacitors, 13-1 to 13-n are AND circuits, 14 is a shift register, 15 is a sample and hold circuit, 16 is a timing selection circuit 17 is an analog buffer circuit, 18-1~
18-n is a buffer circuit, Sl is shift data, CLK
is a shift clock signal, 81 to Sn are shift output signals,
REN, GEN, BEN are enable signals, Q1 to Qn
is the output terminal.

The output terminals Q1 to Qn are connected to a data bus of a matrix display panel (not shown), and the shift register 14 shifts shift data Sl having a length of three cycles of the shift clock signal CLK, and outputs the shifted data Sl. Terminal Q1~Q
In other words, shift output signals 81 to Sn are output corresponding to n data buses of a matrix display panel. Therefore, three shift output signals are outputted temporally overlapping each other. The timing selection circuit 16 is composed of n AND circuits 13-1 to 13-n, and receives three enable signals REN, GEN, and BEN, and a shift register 1.
4 shift output signals 5t-sn are added.

The aforementioned three enable signals REN, GEN.

BEN corresponds to the control signal in FIG. 1. For example, if enable signals RIF, N, GEN, and BEN are set to "1" at the same timing, then, for example, shift output signals St, S2, and 33 are set to timing selection. If added to the circuit 16, the AND circuit 13- of the timing selection circuit 16
The output signals of 1.13-2 and 133 become "1" at the same time, and thereby the sampling switches 11-1.11-2.11-3 of the sample-and-hold circuit 15 are turned on simultaneously, and the R, G, and B signals are turned on. They are simultaneously sampled and held in capacitors 12-1.12-2.12-3.

If the enable signals REN, GEN, and BEN are set to different timings, for example, the shift output signal Sl
, S2. Even if S3 is outputted temporally overlapping, the output signals of the AND circuits 13-1.13-2 and 13-3 become "1" at different timings, so the sampling switch 11-1.11 corresponds to the output signal of the AND circuit 13-1. -2.11-3 are turned on sequentially, and the R, G, and B signals are sequentially sampled and held in the capacitors 12-1.12-2.12-3.

FIG. 3 is an explanatory diagram of sequential sampling according to an embodiment of the present invention, and shows an example of signals having the same symbols and names as those in FIG. 2. Shift data Sl has a length equivalent to three cycles of shift clock signal CLK, and therefore has a length equivalent to three periods of shift clock signal CLK.
When shifted sequentially by LK, the shift output signals St,
In S2.33°..., as shown in the figure, the three shift output signals partially overlap in time. In addition, the enable signals REN, GEN, and BEN are shifted to the clock signal CL.
If the timing is synchronized with K and has a three-phase relationship, then ST
A sampling timing signal indicated by is applied from the timing selection circuit 16 to the sample hold circuit 15, and R,
G and B signals are sequentially sampled.

FIG. 4 is an explanatory diagram of simultaneous sampling. Since the shift data Sl and shift clock signal CLK are the same as those shown in FIG. 3, the shift output signals SL, S2.33.
S4. ... is also the same as the case shown in FIG. Then, enable signal EN (REN=GEN=BEN
), for example, as the shift output signal 31 . S2. By selecting S3 at a free time, a sampling timing signal indicated by ST is applied from the timing selection circuit 16 to the sample hold circuit 15, and the R and GB signals are simultaneously sampled.

Therefore, it can be applied to both sequential sampling and simultaneous sampling.

FIG. 5 is a block diagram of main parts of another embodiment of the present invention,
21 is a sampling switch, 22 is a capacitor, 23
7 is a timing selection switch, 24 is a shift I register, 25a is a number circuit, 25b is a hold circuit,
26 is a timing selection circuit, 27 is an analog buffer circuit, and 28 is a buffer circuit.

The shift register 24 and the analog buffer circuit 27, which shift the shift data Sl in accordance with the shift clock signal CLK and sequentially output the shift output signals 81 to Sn, are the same as those in the previous embodiment.

In this embodiment, a timing selection circuit 2G consisting of a switch 23 such as a transistor is provided between a sample circuit 25a that samples R, G, and B signals and a hold circuit 25b. The signals are sampled by the sampling switch 21 according to the shift output signals 5L-3n of the shift register 24, and the sampling output signals are the enable signals REN, GEN, BE.
The signal is applied to the hold capacitor 22 via the switch 23 controlled by N and held.

Therefore, if enable signals REN, GEN, and BEN are selected in the relationship shown in FIG.
If the relationship shown in FIG. 4 is selected, the R, G, and B signals will be sampled isometrically simultaneously.

FIG. 6 is a block diagram of main parts of still another embodiment of the present invention, in which 31 is a sampling switch, 32 is a capacitor,
33-1.33-2.33-3 is a latch circuit, 34 is a shift register, 35 is a sample hold circuit, 36 is a timing selection circuit, 37 is an analog buffer circuit, 38
Haha, it's a sofa circuit.

A shift register 34, a sample hold circuit 35,
The analog buffer circuit 37 has the same configuration as each of the embodiments described above, and the timing selection circuit 36 receives the launch signals RL and GL.

A latch circuit 33-1.33-2.33-3 that latches the shift output signals S1 to Sn every two bits by BL.
It is made up of.

FIG. 7 is an explanatory diagram of sequential sampling, in which the shift data Sl added to the shift register 34 is assumed to have a length corresponding to one period of the shift clock signal CLK. In synchronization with this shift clock signal CLK, the latch circuit 33 outputs the launch signals RL, OL, and BL at the same timing as shown in FIG.
-1.33-233-3.

Shift output signals St, S2, S3 of the shift register 34
．． . . . is the shift data Sl shifted sequentially according to the shift clock signal CLK, and therefore,
The latch circuit 33-1 has a shift output signal S1. S4.
... are sequentially latched, and the latch circuit 33-2 receives a shift output signal S2. S5, . . . are sequentially latched, and the launch circuit 33-3 receives shift output signals S3. S6.
...will be served for lunch in sequence. Since the latch output signal is applied to the sample hold circuit 35 as a sampling timing signal, IR, IG, I
As shown in B, 2R, . . ., R, G.

This serves as a sampling timing signal for sequentially sampling the B signal.

FIG. 8 is an explanatory diagram of simultaneous sampling, in which the shift data 31 added to the shift register 34 is assumed to have a length equivalent to three cycles of the shift clock signal CLK. Also latch signal RL
, GL, and BL at the same timing every three cycles of the shift clock signal CLK as shown by L in the latch circuit 33-.
1. Add to 33-233-3.

Shift output signals St, S2, S3 of the shift register 34
．． . . . is the result of shifting the shift data Sl sequentially according to the shift clock signal CLK as described above, and as shown in FIG. 3 or 4, the three shift output signals overlap in time. The three shift output signals are respectively sent to latch circuits 33-1.33-2.3.
3-3 are latched at the same time. Therefore, the latch circuit 33
-133-2.Sampling timing signals from 33-3 are IRGB, 2RGB, and 3RGB at the same time.

The signals are outputted as shown by .

Therefore, shift data S1 and latch signals RLGL, B
Depending on the selection of L, sequential sampling and simultaneous sampling can be applied.

Note that sampling of the R, G, and B signals can be performed at the falling timing shown by the arrow of the Usochi output signal.

FIG. 9 is a block diagram of a display device for sequential sampling display, and the matrix display panel 40 has, for example, 243
X240 black and white matrix display panel, 41 is a data bus, 42 is a scan canvas, 43 is a switching element such as a thin film transistor, 44 is a display element such as a liquid crystal, 45 is a synchronous separation circuit, 46 is a color difference signal trap, 4
7 is a buffer amplifier, 48 is a timing control circuit, 49
is a scan driver, and 50-1 to 50-3 are data drivers.

The data drivers 50-1 to 50-3 each have a configuration shown in FIG. 2, FIG. 5, or FIG. 6, are integrated circuits, and are provided in a number corresponding to the display capacity of the matrix display panel 40. For example, the three data drivers 50-1 to 50-3 are responsible for driving 81 of the 243 data buses 41 of the matrix display panel 40. Further, the shift registers of each data driver 50-1 to 50-3 are connected in series, and shift data Sl
is shifted in accordance with shift clock signal CLK.

The video signal is applied to a synchronization separation circuit 45, the separated synchronization signal SYN is applied to a timing control circuit 48, and control signals C3I, C32, such as shift data SI, shift clock signal CLK, enable signal and launch signal,
C33, scan data SD, scan clock signal S
CN etc. are output. Further, in the color difference signal trap 46, the color signal is extracted from the video signal by a 3.58 MHz trap, and the display data is sent to the data drivers 50-1 to 50-3 via the buffer amplifier 47 as a black and white luminance signal. Add as. In this case, the terminals for applying the R, G, and B signals in FIG. 2, FIG. 5, or FIG. 6 are commonly connected to apply the above-mentioned luminance signal.

Further, the scan driver 49 shifts the scan data SD according to the scan clock signal SCN, and sequentially applies scan pulses to the scan canvas 42 using the shift output signal. In synchronization with this scan pulse, one line of data voltage is output from the data drivers 50-1 to 503, and the data bus 41 of the matrix display panel 40
added to.

When the timing selection circuits of the data drivers 50-1 to 50-3 are configured as shown in FIG. 2 or 5, the shift data Sl from the timing control circuit 48 is set to have a length equivalent to three periods of the shift clock signal CLK, 3 control signals C
3I, C32, C33 enable signals REN, GEN
, BEN have the timing relationship shown in FIG.

Thereby, the luminance signals applied from the buffer amplifier 47 to the data drivers 50-1 to 50-3 are sequentially sampled. Further, when the timing selection circuit has the configuration shown in FIG. 6, the timing control circuit 48
The shift data SI from is set to have a length of one cycle of the shift clock signal CLK, and three control signals C3I, C32,
C33 is used as latch signals RL, GL, and BL, and the timing relationship shown in FIG. 7 is established. Thereby, the luminance signals applied from the buffer amplifier 47 to the data drivers 50-1 to 50-3 are sequentially sampled.

In the case of a black-and-white television receiver, if the three dots of R, G, and B are sampled at the same time, the sampling interval will become longer, resulting in a decrease in resolution, but as mentioned above, sampling should be performed sequentially. Since the sampling interval can be shortened, black-and-white display can be performed without reducing the resolution.

FIG. 10 is a block diagram of a display device for simultaneous sampling display, in which 51 is a data bus, 52 is a scan canvas, 5
3 is a switching element, 54 is a display element, 55 is a matrix display panel, 56 is a buffer amplifier, 58 is a timing control circuit, 59 is a scan driver, 60-1 to 6
0-3 are data drivers.

The data drivers 60-1 to 60-3 can each have the configuration shown in FIG. 2, FIG. 5, or FIG.
In the case of a configuration in which the display capacity is 0x200x3 and R, G, and B pixels are arranged in stripes, each data driver 60-1 to 60-3 is required to share and drive 320 data buses 51. become.

Also, R, G, B signals and synchronization signal SYN from a computer etc.
is input, and the timing control circuit 58 outputs shift data SI, shift clock signal CLK, and control signal C3 (three control signals C5I, C3) according to synchronization signal SYN.
2 and C33 at the same timing), scan data SD, scan clock signal SCN, etc. are output. In addition, data drivers 60-1 to 60-1 through the buffer amplifier 56
R, G, and B signals are added to 60-3. Further, a scan pulse is applied from the scan driver 59 to the scan canvas 52 of the matrix display panel 55, and data voltages are applied to the data bus 51 from the data drivers 60-1 to 603 in synchronization with the scan pulse.

The shift registers of the data drivers 60-1 to 60-3 are connected in series as in the previous embodiment, and shift the shift data Sl in accordance with the shift clock signal CLK. If the timing selection circuit of -3 has the configuration shown in FIG. 2 or FIG. As EN (REN, GEN, BEN), R, G, and B signals are sampled using the same sampling timing signal ST. Further, when the timing selection circuit has the configuration shown in FIG. 6, the shift data SI is set to have a length equivalent to three cycles of the shift clock signal CLK, and the control signal CS is set to the latch signal L (RL, GL), as shown in FIG.
, BL), the R, G, and B signals are sampled using the same sampling timing signals IRGB, 2RGB, .

As mentioned above, in the data drivers 60-1 to 603, the R, G, and B signals are sampled simultaneously, and waveform distortion due to the capacitance of the transmission path of the R, G, and B signals is affected. By solving the problem, it is possible to make the matrix display panel 55 perform color display.

FIG. 11 shows the data bus 6 of the matrix display panel 63.
'l on both sides, and the respective data drivers 70-
The block diagram of the display device of division drive display which applies the data voltage by +1 to 1-70- is shown. In the same figure,
62 is a scan canvas, 64 is a timing control circuit, 65
is a scan driver. R, G from a computer, etc.
, B, signals are applied to data drivers 70-1 to 70-, and a synchronization signal SYN is applied to timing control circuit 64. The timing control circuit 64 outputs shift clock signals CLKA, CLKB and control signals C3A, C3.
B, shift data Sl, scan data SD, scan clock signal SCN, etc. are output.

+1 to the data drivers 70-1 to 70- is the second
5 or 6, the shift registers of the odd-numbered and even-numbered data drivers are connected in series, and shift the shift data St in accordance with the shift clock signal CLKACLKB. It is. Also, R, G, B in Figure 2, Figure 5 or Figure 6
Odd numbered data drivers 70-1, 70-3 . ...70- is R-
R, G-B, B→G relationships, and even numbered data drivers 70-2, 70-4. ...70- +l is R
-G, G-R, and B-B, respectively. Also, the control signals C3A, C3B and the enable signal REN,
GEN, BEN or enable signals RL, GL, B
L means odd numbered data drivers 70-1, 70-3.
...For 70-, C5A-BEN (BL)
, C3B → REN.

GEN (RL, GL), even numbered data driver 7
0-2.70-4. ...70-k+1,
C5A-hGEN, BEN (GL, BL), C3B
→REN (RL).

Furthermore, the R, G, and B pixels at the intersection of the data bus 61 and the scan canvas 62 of the matrix display panel 63 are arranged in the order of R, G, B, R, . . . as shown in the circle. Since the data buses 61 are alternately led out to both sides, odd-numbered data buses are connected to odd-numbered data drivers, and even-numbered data buses are connected to even-numbered data drivers. Therefore, the odd numbered data driver 70-
1.70-3. ...From the perspective of 70-k, RlB
, G, R, . . . , and even-numbered data drivers 70-2, 70-4 . ...Looking from +1 to 70-, it's G, R, B, G.

The pixels are arranged in the order of...

When the data drivers 70-1 to 70- have the configuration shown in FIG. 2, they operate according to the control timing shown in FIG. 12. In the figure, St is shift data, CLKA, CLKB are shift clock signals,
C3A and C3B are control signals (enable signals), SIA
, S2A, and S3A are odd-numbered data drivers 70-1.
70-3, . . . 70-, the shift output signals of the shift registers, SIB, S2B, S3B are the even-numbered data drivers 70-2, 70-4, . ...70- shows the shift output signal of the +1 shift register.

The shift clock signal CLKA is applied to the odd-numbered data drivers, and the shift clock signal CLKB is applied to the even-numbered data drivers, and as shown in the figure, their phases are different.

Shift data SI is shift clock signal CL at time t1
The shift data 31 is shifted to the shift register of the data driver 70-1 by KA, and a shift output signal SIA is output, and the shift data 31 is shifted to the shift register of the data driver 70-2 by the shift clock signal CLKB at time t2, and the shift output signal SIA is output. Signal SIB is output, and at time t3
The shift output signal S is generated by the shift clock signal CLKA of
2A is output. At that time, since the control signal C3B is applied to the odd-numbered and even-numbered data drivers, a sampling timing signal indicated by ST is applied to the sample and hold circuit.

For example, in the data driver 70-1, when the control signal C3B becomes "1" at time t3, the enable signal REN,
This corresponds to GEN (see Figure 2) becoming "l", and the shift output signal Sl, 52 (SIA, 52A) becomes '''
1'', the output signal of the AND circuit 13-1.
i.

sampled by 11-2 and connected to capacitor 12-
1.12-2 holds. In addition, in the data driver 70-2, this corresponds to the enable signal REN becoming "1", and only the shift output signal 5l (SIB) becomes "1".
1”, the output signal of the AND circuit 13-1 is “1”.
", and since they are connected in the relationship R-G, GR-R, B→B, the G signal is sampled by the sampling switch 1t-i and held by the capacitor 12-1.

Therefore, the odd-numbered data drivers 70-1 simultaneously sample the R and B signals, and the even-numbered data drivers 70-2 simultaneously sample the G signal.

Similarly, at time t6, shift output signals S2A, S
3A is "1", shift output signal 32B.

33B becomes "l" and the control signal CSA becomes "1", so in the odd numbered data drivers 70-1, the enable signal BEN becomes "1" and the shift 1 output signal S2, 33 becomes "1". Correspondingly, the output signal of the AND circuit 13-3 becomes "1".

Therefore, the G signal is sampled by the sampling switch 11-3 and held in the capacitor 12-3.

In the even-numbered data drivers 70-2, enable signals REN and GEN are "1", and shift output signals S2. S3
Since this corresponds to “1”, AND circuit 13
The output signal of -2.13-3 becomes "1", and the R and B signals are sampled by the sampling switch 11-2.11-3 and held in the condenser 12-2.12-3.

Therefore, in the odd numbered data driver 7o-1, the G signal,
The even-numbered data drivers 70-2 simultaneously sample the R1B signal, and the odd-numbered and even-numbered data drivers alternately sample the R, B, and G signals simultaneously.

Further, in the case of the configuration in which +1 is added to data drivers 70-1 to To- as shown in FIG. 6, control is performed according to the control timing shown in FIG. 13. In this case, the connection relationship between the RG and B signals and the connection relationship between the control signals C3A and C3B are the same as in the above-described embodiment, and the shift clock signals CLKA and CLKB from the timing control circuit 64 have the same timing. shift clock signal CLK is used. Also, the odd numbered data drivers 70-1 receive shift data SIA, and the even numbered data drivers 70-2 receive shift data SIB.
are added and shifted by the shift clock signal CLK at times tl, t2°, etc., so from the shift register of the odd numbered data driver, SIA, S2A
, S3A, . . . are sequentially output from the shift registers of the even-numbered data drivers.
Shift output signals shown as SIB, S2B, S3B, . . . are sequentially output.

Shift output signals SIA, S2A, and SIB are each "1"
” at time t7.l, if the control signal C5B (latch signal) is set to “1”, the odd numbered data drivers 70-
1, the launch signals RL and GL (see Fig. 6) are 'l
”, launch circuit 33-1.33-
The latch output signal of No. 2 is as shown by IRB in FIG. Also, in the even-numbered data drivers 70-2, this corresponds to the latch signal RL becoming 1'', and the launch circuit 33
The launch output signal of -1 is as shown by IG in FIG.

Also, the shift output signals S3A, S2B, and S3B are “
When the control signal SCA is set to "1" at time t4° of "1", the latch signal B
This corresponds to L becoming "1", and the launch circuit 33-3
The latch output signal of is shown in 2G in Fig. 13,
In the even-numbered data drivers 70-2, the latch signal GL
, BL becomes "1", and the latch circuit 33
The latch output signal of 2.33.3 is shown at 2RB in FIG.

Therefore, at the falling timing 15' of the latch output signal, the odd-numbered data drivers 701 sample the R and B signals, and the even-numbered data (, °live buffer 0
-2, the G signal is sampled, and at time t 7 e
In the odd numbered data driver 70-1, G
The signal is sampled and the even numbered data driver 70-
2, the R2B signal will be sampled.

By sequentially repeating the above operations, R, G,
By simultaneously sampling the B signals, a data voltage can be applied to the -matrix display panel 63 to display color.

〔Effect of the invention〕

As explained above, the present invention provides shift output signals St, S2 . ... and three enable signals REN, GEN, BEN or latch signal RL,
A timing selection circuit to which control signals C31C32, C53 such as GL and BL are applied, outputs a sampling timing signal according to the length of shift data Sl and the timing of the three control signals, and adds it to the sample hold circuit 5. 6, the display capacity is relatively small,
In addition, it can be used for both sequential sampling when applied to the matrix display panel 3 for monochrome display, and simultaneous sampling when applied to the matrix display panel 3 for color display, which has a relatively large display capacity. can. Therefore, mass production becomes possible and economy can be achieved.

[Brief Description of the Drawings] Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of main parts of an embodiment of the present invention, and Figs. 3 and 4 are sequential diagrams of an embodiment of the present invention. An explanatory diagram of sampling and simultaneous sampling, FIG. 5 is a block diagram of main parts of another embodiment of the present invention, and FIG.
The figure is a block diagram of main parts of still another embodiment of the present invention, FIGS. 7 and 8 are explanatory diagrams of sequential sampling and simultaneous sampling of still another embodiment of the present invention, and FIG. 9 is a sequential sampling display. A block diagram of a display device, FIG. 10 is a block diagram of a display device with simultaneous sampling display, FIG. 11 is a block diagram of a display device with separate drive display, FIGS.
3 is an explanatory diagram of the control timing of FIG. 11, FIG. 14 is an explanatory diagram of video signals, FIG. 15 is an explanatory diagram of RGB signals, FIG. 16 is a block diagram of main parts of a conventional data driver, and FIG. 17 18 is an explanatory diagram of the operation of the conventional example, FIG. 18 is an explanatory diagram of sequential sampling, and FIG. 19 is a block diagram of main parts of simultaneous sampling. 1 is a data bus, 2 is a scan canvas, 3 is a matrix display panel, 4 is a shift register, 5 is a sample hold circuit, 6 is a timing selection circuit, 7 is an analog buffer circuit, and 8 is a scan driver.

Claims (1)

[Claims] The data bus (1) of a matrix display panel (3) in which a data bus (1) and a scan canvas (2) are orthogonally arranged.
In the data driver of the matrix display device that applies a data voltage to the data driver, shift data is shifted according to the shift clock signal,
a shift register (4) that sequentially outputs shift output signals corresponding to the data bus (1); a sample hold circuit (5) that samples display data and outputs the data voltage corresponding to the data bus (1); The shift output signal of the shift register (4) and three control signals are added, and the length of the shift data and the three control signals are added.
A data driver for a matrix display device, comprising a timing selection circuit (6) for applying a sampling timing signal according to the timing of each control signal to the sample and hold circuit (5).