JPH0282331A - Cache memory control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control method, and in particular, a high-speed hit/miss determination method for a cache memory suitable for high-speed operation of a microprocessor, etc. [Prior Art] Conventionally, Regarding the cache memory control method, as described in Nikkei Electronics, January 13, 1986 issue (No. 386), pages 204 to 207, the main memory is divided into multiple sets, and the The cache memory is divided into several blocks, and the cache memory stores the data contained in each block and the address (
The data stored in the cache memory is determined by the address attached to the set (hereinafter referred to as the set address) to determine whether or not data in the main memory exists in the cache memory. This is done by reading out the tag address given by the data processing device and comparing it with the tag address given by the data processing device. In this case, if the comparison results match (this is called a cache hit), the desired data exists in the cache memory, and if they do not match (this is called a cache miss), the desired data exists in the cache memory. indicates that the desired data does not exist. FIG. 3 shows the configuration of a conventional cache memory.

When increasing the cache memory capacity to improve the cache hit rate, set associative or direct mapping methods are adopted due to hardware limitations.
OFFSET) as well as the physical page number whose address has been translated. A part of the address is also used as an address to check the tag memory, and hit/miss determination is performed.

[Problem to be solved by the invention]

”1 In the conventional technology, the cache memory hit/miss result is converted from a logical address to a physical address and determined after searching the tag memory. However, there is a problem in that the execution time of the data processing device is limited. Especially in recent years, with the development of LSI technology,
As data processing devices, especially microprocessors, become faster and the execution time of one instruction approaches the cache memory access time, the cache memory hit/run time increases.
Unless the mishit determination is performed at high speed, the performance of the data processing device cannot be fully exploited.

An object of the present invention is to provide a cache memory control method that can perform this hit/miss judgment at high speed and make full use of the performance of a data processing device.

[Means to solve the problem]

The above purpose is to
In most cases, we focus on the locality of the program, which means that instructions near the executed instruction are executed, and search for the last accessed page number. This is achieved by holding the register in a register, searching the tag memory using this register output and 0FFSET, which is not converted into an address, and determining a hit/miss.

[Effect]

Last accessed page no. The register always outputs the address for the cache memory, and in parallel with the tag memory search based on the output of the logical address from the data processing device, the result of address translation is the last accessed page number. are compared, a matching result is output, and the tag memory and previous access page number are stored. When both registers are set, data is sent to the data processing device.

In this way, the tag search and address conversion can be processed in parallel, and it is possible to quickly determine if there is a hit/miss.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows the configuration of a cache memory device constructed using the present invention, and FIG. 2 shows the configuration of a CPU using this cache memory device. The cache memory device 20 is
It is placed between the data processing device 7 and the main memory 9 and operates as a high-speed buffer of the main memory. Further, the cache memory device 20 includes a cache memory 2, a tag comparator 5 for performing hit/miss determination, and the like. In FIG. 1, the cache memory 2 includes a tag address storage section (tag memory) that indicates at which address in the main memory the data is copied, and a data storage section (data memory 1) that stores the data.
month and V indicating whether the data in the data storage section is valid or not
Consists of a flag section.

The address (logical address) output from the data processing device is the logical page number. and 0FFSET address. In recent data processing devices, one page has IK to 8 bytes.

Logical page no. is converted by the address conversion circuit 1 into a physical page Nn indicating an actual page on the main memory. When the content tag j of the tag section of the cache memory 2 searched using the lower part of this physical address is compared with the upper part of the address by the tag comparator 5, it is determined to be a hit, and the block at the lower address that is not involved in tag determination is determined to be a hit. When the data selection circuit 22 selects desired data from the data i attached to one tag 1 according to the address, and the corresponding V flag indicating validity is set, the
6 is returned as a response signal to the data processing device 7, and at the same time, the output of the data selection circuit 22 is sent back to the data processing device 7.
will be returned to. Next, if the tag comparator 5 determines that there is a miss, or if the corresponding flag (2) is not set, the AND circuit 6 determines that it is a cache miss, and sends the data to the data processing device 7. It does not return a response, but requests the bus interface circuit 8 to bring data from the main memory 9. This request signal is connected to the bus interface circuit 8 via a NOT gate 81 as an inverse response to the data processing device 7 . The above cache memory operation is well known. In addition to the configuration of the conventional cache memory, the cache memory device 20 according to the present invention retains a part of the previously accessed physical page H[l, and the previously accessed page whose output becomes part of the index address for cache tag memory search. No.
Register 3, this register output, and physical page number.
An access page comparator 4 is provided for determining whether a portion of the numbers are equal, and the output of this comparator 4 is also input to the ant games 1 and 6 that output hit/miss hints.

Next, the operations of the above two circuits will be mainly described.

First, when there is an access from the data processing device 7, a part of the physical page number whose address has been translated is stored in the previously accessed page number register 3.

Next, when there is another access from the data processing device 7, the tag memory is searched using the output of the previously accessed page number register 3 and 0FFSET whose address is not translated, and in parallel with this search, the physical page that has passed through the address translation circuit 1 is searched. No. A part of the page is the last accessed page No. The output of the register 3 is compared with the access page comparator 4. When the output of the access page comparator 4, the output of the tag comparator 5, and the ■ flag all indicate hit and valid,
It is determined that there is a cache memory hit. Last accessed page no. At the end of this access, the physical page number 31E is stored in register 3. A part of is set and prepared for the next access. The cache memory 2 may have an intermediate cache memory for instructions and a cache memory for operands in order to access different addresses and improve the hit rate. In this case, the last accessed page No. It is also possible to provide a register 3 and an access page comparator 4 for instructions and operands, respectively. This embodiment is shown in FIG. or,
Cache memory 2 has one set of 1-, but the last accessed page No. It is also possible to have a register 3 and an access page comparator 4 for instructions and operands, respectively, and select the output based on a signal from the data processing device 7 indicating whether the instruction access or data access is to be used for tag memory search.

In this case, as shown in FIG. 5, selectors 31 and 41 are provided to select one of them.

Further, as shown in FIG. 6, the access page comparator 4 has 1
It is also possible to set the number to set 1-.

According to this embodiment, 0FFSET whose address is not translated
Department and last accessed page no. Since the tag memory is searched using the contents of the register as an index address, the tag memory tag comparator → AND gate can be used for determination from the time the data processing device 7 starts accessing until the hit/miss determination is made, and the address conversion circuit Hit/miss determination can be performed faster by one conversion time.

〔Effect of the invention〕

According to the present invention, while employing a physical cache configuration, address translation time can be omitted from cache hit determination time.
This has the effect of allowing high-speed hit/mishit determination.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of a CPU using the present invention, FIG. 3 is a diagram showing an example of a conventional cache memory device, and FIG. FIG. 5 and FIG. 6 are examples of application of the present invention. 1...Address conversion circuit, 2...Cache memory, 3...Previously accessed page register, 4...Accessed page comparator, 5...Tag comparator, 20...Catch Chaotsuro

Claims (1)

[Claims] 1. Logical page number. Of the logical addresses consisting of the offset address and the logical page number. physical page number.
a physical cache memory having a tag memory for storing page addresses and a data memory for storing data in units of pages; In a cache memory control method that includes a tag comparing means for comparing the converted physical page No. Previously accessed page No. is temporarily stored. register and the previous access page number. Register output and current physical page number. Physical page No. to be compared. It has a comparison means, and the previous access page No.
The content of the tag memory to be output to the tag comparison means is read using the register and the offset address that is not converted, and the output of the tag comparison means and the corresponding physical page number are read.
．． A cache memory control method characterized in that a hit or a miss in a physical cache memory is determined based on the output of a comparing means. 2. Logical page number. Among the logical addresses consisting of the offset address and the logical page No. The physical page no.
．． a physical cache memory having a tag memory for storing page addresses and a data memory for storing data in units of pages; In the cache memory control method, the cache memory control method includes a tag comparison means for comparing the previous physical page No. Previously accessed page No. that latches part of the page. It has a register, and the previous access page number. A cache memory control method characterized in that a physical cache memory is accessed using a register output and an off-address that is not converted. 3. Physical page number whose address has been translated. It has a physical cache consisting of a tag memory and a data memory that are accessed by an offset address that is not converted, and the contents read from the tag memory and the physical page number are
．． In a cache memory control method that determines a hit or miss in a physical cache memory based on the relationship, the previous physical page No. is temporarily latched, and this latched last accessed physical page No. The physical cache is accessed using the offset address and the previously accessed physical page No. And this time's physical page No. A cache memory control method characterized in that access to the physical cache is enabled when the values are equal. 4. When accessing the physical cache memory after converting a logical address into a physical address, the physical page number whose address was converted in the previous step. The physical cache is accessed using the offset address that is not translated, and the previous physical page number is accessed. and the current physical page no. A cache memory control method characterized in that access to the physical cache memory is enabled when the values are equal. 5. In claim 1, the physical cache memory is divided into instructions and operands, and the previously accessed page number is stored in correspondence with each one. Register and physical page number. A cache memory control method characterized by providing a comparison means. 6. In claim 1, the last accessed page No. Register and physical page number. Comparing means are provided for instructions and operands respectively, and the previously accessed page number is determined by a signal line indicating whether the access is an instruction access or an operand access from the data processing device. Register and physical page number. A cache memory control method characterized in that a comparison means is selected and a physical cache memory is accessed.