JPH028247U - - Google Patents

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Publication number
JPH028247U
JPH028247U JP8746088U JP8746088U JPH028247U JP H028247 U JPH028247 U JP H028247U JP 8746088 U JP8746088 U JP 8746088U JP 8746088 U JP8746088 U JP 8746088U JP H028247 U JPH028247 U JP H028247U
Authority
JP
Japan
Prior art keywords
clock
opposite
retiming
speed
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8746088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8746088U priority Critical patent/JPH028247U/ja
Publication of JPH028247U publication Critical patent/JPH028247U/ja
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案による多重分離装置の一例を
示すブロツク図、第２図はその動作の説明に供す
るためのタイムチヤート、第３図は従来の多重分
離装置を示すブロツク図、第４図はその動作の説
明に供するためのタイムチヤートである。 FIG. 1 is a block diagram showing an example of a demultiplexing device according to this invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block diagram showing a conventional demultiplexing device, and FIG. This is a time chart for explaining its operation.

Claims (1)

【実用新案登録請求の範囲】 入力信号と、これと同速度のクロツク信号とが
与えられ、互いに逆位相の信号を出力するリタイ
ミング回路と、 上記クロツク信号を分周し、同一速度で逆位相
の低速クロツクを発生する分周回路と、 上記互いに逆位相の信号がデータ端子へそれぞ
れ供給され、上記逆位相の低速クロツクがクロツ
ク端子へそれぞれ供給されてリタイミングをとる
第１、第２Ｄ形フリツプフロツプとを具備する多
重分離装置。[Claims for Utility Model Registration] A retiming circuit that is given an input signal and a clock signal at the same speed and outputs signals with opposite phases to each other; a frequency divider circuit that generates a low-speed clock; and first and second D-type flip-flops, each of which receives the opposite-phase signals to its data terminal, and supplies the opposite-phase low-speed clock to its clock terminal for retiming. A demultiplexing device comprising:
JP8746088U 1988-06-29 1988-06-29 Pending JPH028247U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8746088U JPH028247U (en) 1988-06-29 1988-06-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8746088U JPH028247U (en) 1988-06-29 1988-06-29

Publications (1)

Publication Number Publication Date
JPH028247U true JPH028247U (en) 1990-01-19

Family

ID=31312073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8746088U Pending JPH028247U (en) 1988-06-29 1988-06-29

Country Status (1)

Country Link
JP (1) JPH028247U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58195335A (en) * 1982-05-10 1983-11-14 Nec Corp Data separating circuit
JPS6346833A (en) * 1986-08-14 1988-02-27 Nec Corp Signal separation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58195335A (en) * 1982-05-10 1983-11-14 Nec Corp Data separating circuit
JPS6346833A (en) * 1986-08-14 1988-02-27 Nec Corp Signal separation circuit

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