JPH0283607A - Erroneous loading preventing system - Google Patents

Abstract

PURPOSE:To automatically detect erroneous loading by outputting a response signal to a central processing unit by a judging means based on the identification of an identification means. CONSTITUTION:A connection means 115 connects the central processing unit 111 to a signal supply means 113 electrically, and also, supports them mechanically, and is provided with the identification means 116 which identifies whether or not the signal supply means 113 is loaded at a desired position. The signal supply means 113 is operated based on a signal introduced from the central processing unit 111, and is provided with the judging means 117 which outputs the response signal to the central processing unit 111 based on the identification of the identification means 116. The judging means 117 included in the signal supply means 113 outputs the response signal to the central processing unit 111 based on the identification of the identification means 116 when the signal supply means 113 is loaded at the desired position of the connection means 115. In such a way, it is possible to automatically detect the erroneous loading.

Description

[Detailed Description of the Invention] [Summary] Regarding an incorrect mounting prevention method that prevents incorrect mounting when installing electrical components, the present invention aims to automatically detect incorrect mounting, and the purpose is to automatically detect incorrect mounting. The signal supply means that operates based on the introduced signal and the central processing unit and the signal supply means are electrically connected.
and a mechanically supporting connection means, the connection means has identification means for identifying whether or not the signal supply means is mounted at a desired position, and the signal supply means is configured to identify whether or not the signal supply means is mounted at a desired position. 1. A method for preventing erroneous mounting, characterized by comprising a determining means for outputting a response signal to a central processing unit if the signal supply means is mounted at a desired position based on identification.

[Industrial application field]

The present invention relates to a method for preventing erroneous mounting, and particularly to a method for preventing erroneous mounting that prevents erroneous mounting when mounting electrical components.

[Conventional technology]

When electrical parts and elements that need to be easily replaced are connected to other equipment via a so-called bank board that provides electrical connection and mechanical support, the mounting position on the backboard. may be specified.

For example, in a storage device consisting of a main storage device and an auxiliary storage device, high-speed memory is used for the main storage device that is frequently used due to cost considerations, and low-speed memory is used for the auxiliary storage device that is used less frequently. In this case, since the characteristics of the memory used in the storage device vary depending on the purpose, the mounting positions of electrical components and the like to be mounted on the backboard are specified. Also, when implementing the system, the person in charge is careful when implementing it.

[Problem to be solved by the invention]

However, during mounting, human error may cause the mounting position to be incorrect. For example, a high-speed memory is connected for auxiliary storage and a low-speed memory is connected for main storage. In this case, there is a problem that the central processing unit operates without being able to detect this implementation error, resulting in a decrease in processing efficiency.

The present invention was created in view of the above points, and an object of the present invention is to provide a method for preventing erroneous mounting that automatically detects erroneous mounting.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the erroneous mounting prevention method of the present invention.

In the figure, the connection means 115 is a central processing unit], I
1 and the signal supplying means 113, and mechanically supporting the signal supplying means 113, the identification means 116 identifies whether or not the signal supplying means 113 is mounted at a desired position.

The signal supply means 113 operates based on a signal introduced from the central processing unit 111, and responds to the central processing unit 111 if the signal supply means 113 is mounted at a desired position based on the identification by the identification means 116. It has a determining means 117 that outputs a signal.

Therefore, as a whole, if the signal supply means 113 is mounted at a desired position, the determination means 117 and the central processing unit 11
A response signal is output to 1.

[For production]

The signal supply means 113 is connected to the central processing unit 111 via the connecting means 115 and operates based on signals introduced from the central processing unit 111.

The determining means 117 included in the signal supplying means 113 determines, based on the identification by the identifying means 116 included in the connecting means 115,
When the signal supply means 113 is installed at a desired position of the connection means 115, it outputs a response signal to the central processing unit 111.

In the present invention, based on the identification by the identification means 116,
Since the determining means 117 outputs a response signal to the central processing unit flll, incorrect mounting can be automatically detected.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows a block diagram of an embodiment that employs the incorrect loading prevention method according to the present invention.

(2) Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The signal supply means 113 corresponds to the high speed memory section 211 and the low speed memory section 221.

The connecting means 115 corresponds to the backboard 231.

The identification means 116 includes a terminal 237 which is a grounded terminal;
, corresponds to the terminal 237□ in the open state.

The determining means 117 is a tri-state buffer 215
．． Terminal 21L, terminal 217□, response signal generation circuit 219
．． ) live state buffer 225, terminal 227 . ,
Terminal 2277. This corresponds to the response signal generation circuit 229.

Central processing unit 111 is not shown.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

2. Configuration of the Embodiment In FIG.
, a backboard 231, and a central processing unit (not shown).
CPU).

The high-speed memory unit 211 includes a resistor 213, a tri-state buffer 215 that determines whether it is mounted at a desired position, and a terminal 217 that connects to the backboard 231.
1, a terminal 217□ that returns a response signal to the CPU, and a terminal 217□ that returns a response signal to the CPU.
A response signal generation circuit 219 that generates a response signal to U is provided.

The low-speed memory unit 221 includes a resistor 223, a tri-state sensor 225 that determines whether it is mounted at a desired position, and a terminal 22 that connects to a backboard 231.
71, a terminal 227□ that returns a response signal to the CPU, and c
A response signal generation circuit 229 that generates response signals to p and u
Equipped with

The backboard 231 includes a basic section 233 on which a high-speed memory section 211 is mounted, and an extension section 235 on which a low-speed memory section 221 is mounted.

In the high-speed memory section 211, the output control input terminal of the tri-state buffer 215 is connected to the terminal 2171, and the voltage V, (for example, 5 volts) is connected to the resistor 2.
It is inverted and applied via 13. The input terminal of the tri-state buffer 215 is the response signal generation circuit 219
The output terminal is connected to CP via terminal 217□.
Connected to U.

In the low-speed memory section 221, the output control input terminal of the tri-state buffer 225 is connected to the terminal 227I, and a voltage V, (for example, 5 volts) is connected to the resistor 2.
23.

The input terminal of the tri-state buffer 225 inputs the output of the response signal generation circuit 229, and the output terminal is connected to the terminal 22.
Connected to the CPU via 7□.

The basic portion 233 of the puncture board 231 includes a grounded terminal 2371, and the extension portion 235 includes an open terminal 237□.

(2) Operation of the Embodiment In the above-described incorrect installation prevention system, the high-speed memory section 211 and the low-speed memory section 221 have the output control input signals of the tri-state buffers 215 and 225 at a logic level "'". ” Set it to work in °.

Here, the basic unit 233 to which the high-speed memory unit 211 should be connected
terminal 237. is grounded. Further, the terminal 237□ of the expansion section 235 to which the low-speed memory section 221 is to be connected is in an open state. High speed memory section 211 and low speed memory section 221
When the tri-state buffer 215 is mounted at a desired position on the backboard 231, the high-speed memory section 211 has the terminal 2171 grounded and the tri-state buffer 215
The logic level of the output control input signal is “low’°, but
Since it is an inverted input, the logic level acts as "high °".In addition, in the low-speed memory section 221, the terminal 227
1 is open, so the logic level of the output control input signal of tri-state buffer 225 is "high".

When the output control input signal is at a high logic level, tri-state buffers 215 and 225 operate and output a signal having the same polarity as the input signal. That is, the outputs of the response signal generation circuits 219 and 229 are outputted from the corresponding terminals 217□ and 227□, respectively.

If the connection is reversed, the high-speed memory section 211
The logic level of the output control input signal of the state buffer 215 is "high", but since it is inverted, the logic level acts as "°low".

In the low-speed memory section 221, the terminal 2271 is grounded, so that the logic level of the output control input signal of the tri-state buffer 225 becomes "low". The outputs of the three tri-state buffers 215 and 225 have high impedance, and the response signal generation circuit 2 to which they are connected
The outputs of 19 and 229 are not output to CP[J.

■Summary of Examples In this way, the CPU can be installed in the high-speed memory section 211,
It can be determined that there is no response signal from the low-speed memory section 221. If erroneous mounting is detected, no operation is performed under the control of the CPU, so it can be corrected, and processing efficiency will not be reduced due to operation without being able to detect erroneous mounting.

(9) Modifications of the Invention The above-described embodiments of the present invention relate to a storage device, but a plurality of other electrical components may be mounted.

In addition, in ``correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art can easily imagine that the present invention is not limited to this and that there are various modifications.

[Effects of the Invention] As described above, according to the present invention, the determination means outputs a response signal to the central processing unit based on the identification by the identification means, so that incorrect mounting can be automatically detected, which is practical. is extremely useful.

[Brief explanation of the drawing]

FIG. 1 is a basic diagram of the method for preventing erroneous loading according to the present invention, and FIG. 2 is a diagram showing the configuration of an embodiment employing the method for preventing erroneous loading according to the present invention. In the figure, 111 is a central processing unit, 113 is a signal supply means, 115 is a connection means, 116 is an identification means, 117 is a judgment means, 211 is a high-speed memory section, 21.3 and 223 are resistors, and 215.225 are try-outs.・State buffer, 217
．． 227 and 327 are terminals, 219 and 229 are response signal generation circuits, 221 is a low-speed memory section, 213 is a backboard, 233 is a basic section, and 235 is an extension section. Figure 1

Claims (1)

[Claims] (1) A signal supply means (113) that operates based on a signal introduced from a central processing unit (111), and a mechanical device that electrically connects the central processing unit (111) and the signal supply means (113) and and a connection means (115) that supports the signal supply means (113).
) is mounted at a desired position, and the signal supply means (113) includes an identification means (116) for identifying whether or not the identification means (116) is mounted at a desired position.
), if the signal supply means (113) is mounted at a desired position, the determination means (117) outputs a response signal to the central processing unit (111). Features a method to prevent incorrect loading.