JPH0283965A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0283965A JPH0283965A JP63234850A JP23485088A JPH0283965A JP H0283965 A JPH0283965 A JP H0283965A JP 63234850 A JP63234850 A JP 63234850A JP 23485088 A JP23485088 A JP 23485088A JP H0283965 A JPH0283965 A JP H0283965A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- resistor
- schottky barrier
- barrier diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 1
- 239000002574 poison Substances 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ポリシリコン抵抗と該ポリシリコン抵抗に直
接接続するショットキーバリアダイオドを備えた半導体
集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit including a polysilicon resistor and a Schottky barrier diode directly connected to the polysilicon resistor.
第５図、第６図はそれぞれ従来の半導体集積回路におけ
るポリシリコン抵抗、ショットキーバリアダイオードの
構造の一例を示す。FIGS. 5 and 6 respectively show examples of structures of a polysilicon resistor and a Schottky barrier diode in a conventional semiconductor integrated circuit.
図において１はｎ−エピタキシャル層、２は低濃度ポリ
シリコン層、３は５ｉ０２膜、４は高濃度ポリシリコン
層、５Ｈｐアインレ一シヨン拡散層、６はｎ−を散層、
７はＡｔ膜である。In the figure, 1 is an n- epitaxial layer, 2 is a low-concentration polysilicon layer, 3 is a 5i02 film, 4 is a high-concentration polysilicon layer, a 5Hp inlay diffusion layer, 6 is an n- dispersed layer,
7 is an At film.
ポリシリコン抵抗は、ｎ−エピタキシャル層１上にポリ
シリコン層を生成、低濃度のイオン打込みを行い、抵抗
体とする低濃度ポリシリコン層２を形成し、抵抗体２の
両端にＡｔ膜７を高濃度７リシリコ、ン層４を挿んで接
着し、オーミック接続させて電極を形成したものであり
、ショットキー・シリアダイオードは、Ｐ”フインレー
ション拡散層５に囲われたアイランド内のｎ−エピタキ
シャル層１にＡｔ ７、ｐｔなどを接触させたものであ
る。For the polysilicon resistor, a polysilicon layer is formed on the n-epitaxial layer 1, ions are implanted at a low concentration, a low concentration polysilicon layer 2 is formed as a resistor, and an At film 7 is placed on both ends of the resistor 2. A Schottky serial diode is formed by inserting and bonding a high-concentration 7 silicon layer 4 and making an ohmic connection to form an electrode. Layer 1 is in contact with At 7, PT, etc.
従来、半導体集積回路で、ポリシリコン抵抗とショット
キーバリアダイオードを直列に直接接続する場合、上記
構造のポリシリコン抵抗とショットキーバリアダイオー
ドをＡｔ配線で接続する構造を採ってきた。Conventionally, when a polysilicon resistor and a Schottky barrier diode are directly connected in series in a semiconductor integrated circuit, a structure has been adopted in which the polysilicon resistor and the Schottky barrier diode having the above structure are connected by an At wiring.
従来のポリシリコン抵抗とショットキーバリアダイオー
ドを直接接続した回路部分で、直接接続するメリットが
取り入れられておらず、ショットキーパリアダイオード
を他の素子と分離するためのアイソレーション拡散層５
が、省スペース化の障害となっていた。This is a circuit part where a conventional polysilicon resistor and a Schottky barrier diode are directly connected, but the benefits of direct connection are not incorporated, and an isolation diffusion layer 5 is used to separate the Schottky barrier diode from other elements.
However, this was an obstacle to space saving.
本発明は、上記の問題を解消するためＫなされたもので
、上記回路の省スペース化を計り、集積度を上げること
を目的とする。The present invention has been made to solve the above-mentioned problems, and aims to save the space of the above-mentioned circuit and increase the degree of integration.
本発明は、ポリシリコン抵抗の抵抗体の低ｉｊ１度ポリ
シリコン層をショットキー・マリアグイオードの半導体
領域層とすることで、ショットキーバリアダイオードを
他の素子と分離するアイソレーション拡散層を必要とし
なくしたものである。The present invention uses the low ij 1 degree polysilicon layer of the resistor of the polysilicon resistor as the semiconductor region layer of the Schottky barrier diode, thereby eliminating the need for an isolation diffusion layer that separates the Schottky barrier diode from other elements. This is what I lost.
第１図（ａ） 、 （ｂ）は本発明の一実施例の構造を
示し、各符号は第５図、第６図の同一符号と同一または
相当する部分を示す。FIGS. 1(a) and 1(b) show the structure of an embodiment of the present invention, and each reference numeral indicates the same or corresponding part to the same reference numeral in FIGS. 5 and 6. FIG.
ｎ−エピタキシャル層１上に、ポリシリコン抵抗の抵抗
体とする低濃度ポリシリコン層２を形成し、この低濃度
プリシリコン層２の一方のコンタクト部を高濃度−リシ
リコン層４を挿んでＡｔ膜７にオーミック接続させ、も
う一方のコンタクト部では、低濃度ポリシリコン層２を
直接Ａｔ膜７に接触させ、ショットキーバリアダイオー
ドを形成したものである。On the n-epitaxial layer 1, a low-concentration polysilicon layer 2 is formed as a resistor for a polysilicon resistor, and one contact part of this low-concentration pre-silicon layer 2 is covered with an At film by inserting a high-concentration polysilicon layer 4. At the other contact portion, the low concentration polysilicon layer 2 is brought into direct contact with the At film 7 to form a Schottky barrier diode.
上記構造にすること釦よって、ポリシリコン抵抗の領域
だけですみ、ショットキルバリアダイオード用の領域が
必要でなくなり、大幅な省スに一スになる。By adopting the above structure, only the area for the polysilicon resistor is required, eliminating the need for an area for the Schottkill barrier diode, resulting in significant savings.
第２図は第１図に示す部分の構成回路を示す。FIG. 2 shows the configuration circuit of the portion shown in FIG.
第３図は入力端子サージ保護回路の一例を示し、第４図
は第３図に示す回路に本発明を適用した実施例を示し、
各符号ｆ′ｉ第１図の同一符号が示す部分に相当する部
分を示す。FIG. 3 shows an example of an input terminal surge protection circuit, and FIG. 4 shows an embodiment in which the present invention is applied to the circuit shown in FIG.
Each reference numeral f'i indicates a part corresponding to the part indicated by the same reference numeral in FIG.
従来の場合に比べ、狭い領域にサージ保護回路を実現で
きる。Compared to the conventional case, the surge protection circuit can be implemented in a narrower area.
以上説明したように、本発明によれば、従来のものに比
べ、かなり狭い領域に抵抗とショットキーバリアダイオ
ードを直接接続する回路部分を実現でき、集積度を上げ
ることができるという効果がある。As explained above, according to the present invention, it is possible to realize a circuit portion in which a resistor and a Schottky barrier diode are directly connected in a considerably narrower area than in the conventional circuit, and the degree of integration can be increased.
９４１図（ａｌ 、 （ｂ） ＃ｉ本発明の一実施例を
示す平面図、断面図、第２図は第１図に示す部分の構成
回路を示す回路図、第３図は入力端子サージ保護回路の
一例を示す回路図、第４図＆″ｉ第３図忙示す回路に本
発明を適用しｆｃ実施例を示す平面図、第５図、第６図
はそれぞれ従来の半導体集積回路における、４ リシリ
コン抵抗、ショットキーバリアダイオードの構造の一例
を示す断面図である。
１・・・ｎ〜エピタキシャル層、２・・・低濃度ポリシ
リコン層、３・・・Ｓ＋０２Ｍ、４・・・高濃度ポリシ
リコン層、５・・・ｐ＋アイソレーション拡牧層、６・
・・ｎ＋拡散層、７・・・Ａｔ膜
なお図中同一符号は同一または相当する部分を示す。
１ｎ−エピタキシャル層
ｊ１１図
＋キーーー
第２図
特許出願人 新日本無線株式会社
毒
第３図Figure 941 (al, (b) #i A plan view and a sectional view showing an embodiment of the present invention, Figure 2 is a circuit diagram showing the configuration circuit of the part shown in Figure 1, Figure 3 is an input terminal surge protection FIG. 4 is a circuit diagram showing an example of the circuit, FIG. 3 is a plan view showing an FC embodiment in which the present invention is applied to the circuit shown in FIG. 4 is a cross-sectional view showing an example of the structure of a silicon resistor and a Schottky barrier diode. 1... n~ epitaxial layer, 2... low concentration polysilicon layer, 3... S+02M, 4... high concentration polysilicon layer. Polysilicon layer, 5...p+ isolation expansion layer, 6.
. . . n+ diffusion layer, 7 . . At film. In the drawings, the same reference numerals indicate the same or corresponding parts. 1n-epitaxial layer j11 diagram + key - Figure 2 Patent applicant New Japan Radio Co., Ltd. Poison Figure 3
Claims (1)
濃度ポリシリコン層の一方のコンタクト部に低濃度ポリ
シリコン層表面に直接金属を接触させて形成したショッ
トキーバリアダイオードを備えた半導体集積回路。A semiconductor integrated circuit comprising a polysilicon resistor and a Schottky barrier diode formed by directly contacting metal to the surface of the low concentration polysilicon layer at one contact portion of the low concentration polysilicon layer of the resistor of the polysilicon resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63234850A JPH0283965A (en) | 1988-09-21 | 1988-09-21 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63234850A JPH0283965A (en) | 1988-09-21 | 1988-09-21 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0283965A true JPH0283965A (en) | 1990-03-26 |
Family
ID=16977335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63234850A Pending JPH0283965A (en) | 1988-09-21 | 1988-09-21 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0283965A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008177466A (en) * | 2007-01-22 | 2008-07-31 | Epson Imaging Devices Corp | Display unit and electronic device having the same |
-
1988
- 1988-09-21 JP JP63234850A patent/JPH0283965A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008177466A (en) * | 2007-01-22 | 2008-07-31 | Epson Imaging Devices Corp | Display unit and electronic device having the same |
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