JPH0284768A - Manufacture of solid-state image sensing element - Google Patents
Manufacture of solid-state image sensing elementInfo
- Publication number
- JPH0284768A JPH0284768A JP63237707A JP23770788A JPH0284768A JP H0284768 A JPH0284768 A JP H0284768A JP 63237707 A JP63237707 A JP 63237707A JP 23770788 A JP23770788 A JP 23770788A JP H0284768 A JPH0284768 A JP H0284768A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- gate insulating
- insulating film
- charge transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract 7
- 239000010703 silicon Substances 0.000 claims abstract 7
- 239000012212 insulator Substances 0.000 claims abstract 5
- 238000003384 imaging method Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 8
- 239000011574 phosphorus Substances 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 18
- 230000007547 defect Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005247 gettering Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は固体撮像素子の製造方法に関し、特に２層多結
晶シリコン構造を有する電荷結合素子（ＣＯＤ）の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a solid-state imaging device, and particularly to a method for manufacturing a charge-coupled device (COD) having a two-layer polycrystalline silicon structure.
従来、この種の２層多結晶シリコン電極構造の電荷結合
素子を用いた固体撮像素子は、第３図に平面図、第４図
（ａ）に第３図のＩ−１層面の断面図、第４図（ｂ）に
第３図のｎ−ｎ’面の断面図を示した様に、Ｐ型半導体
基板１にＰ−Ｎ接合により形成した複数個の光電変換部
２と、信号電荷を転送するＮ型領域６、ゲート絶縁膜１
０及び２層の多結晶シリコン膜１１．１２から成る電荷
転送部３と、光電変換部２から電荷転送部３へ信号電荷
を読み出すトランスファゲート部４と隣接した光電変換
部２及び電荷転送部３を電気的に分離するチャンネルス
トップ５とを有していた。Conventionally, a solid-state imaging device using a charge-coupled device with a two-layer polycrystalline silicon electrode structure of this type has a plan view shown in FIG. 3, a cross-sectional view of the I-1 layer plane in FIG. As shown in FIG. 4(b), which is a cross-sectional view taken along the n-n' plane in FIG. N-type region 6 to be transferred, gate insulating film 1
The photoelectric conversion section 2 and the charge transfer section 3 are adjacent to a transfer gate section 4 that reads signal charges from the photoelectric conversion section 2 to the charge transfer section 3. It had a channel stop 5 for electrically isolating the.
第５図は従来の固体撮像素子の主な製造工程における電
荷転送部の断面図の一例である。Ｐ型半導体基板１内に
選択的に光電変換部２と、電荷転送部３の埋込チャンネ
ルとなるＮ型層６及びチャンネルストップ５となる高濃
度のＰ型層７を形成した後Ｐ型半導体基板１を酸化して
第１のゲート絶縁膜８を形成し、第１の多結晶シリコン
膜１１を堆積させ、第１の多結晶シリコン膜の比抵抗を
下げる為及びＰ型半導体基板ｌの裏面に高濃度のりんを
入れて結晶欠陥を裏面に意図的に発生させゲッタリング
を行う為に前記第１の多結晶シリコン膜１１にリンを拡
散する（第５図（ａ））。FIG. 5 is an example of a cross-sectional view of a charge transfer section in the main manufacturing process of a conventional solid-state image sensor. After selectively forming a photoelectric conversion part 2 in a P-type semiconductor substrate 1, an N-type layer 6 which becomes a buried channel of a charge transfer part 3, and a high concentration P-type layer 7 which becomes a channel stop 5, a P-type semiconductor is formed. A first gate insulating film 8 is formed by oxidizing the substrate 1, and a first polycrystalline silicon film 11 is deposited to lower the resistivity of the first polycrystalline silicon film and to reduce the resistivity of the first polycrystalline silicon film and to form a first gate insulating film 8 on the back surface of the P-type semiconductor substrate l. A high concentration of phosphorus is introduced into the first polycrystalline silicon film 11 to intentionally generate crystal defects on the back surface and to perform gettering, phosphorus is diffused into the first polycrystalline silicon film 11 (FIG. 5(a)).
次に写真食刻法及びプラズマエツチング法により第１の
多結晶シリコン膜をパターニングし、前記第１のゲート
絶縁膜８をフッ酸系エツチング液にて基板表面までエツ
チングする（第５図（ｂ））。Next, the first polycrystalline silicon film is patterned by photolithography and plasma etching, and the first gate insulating film 8 is etched down to the substrate surface using a hydrofluoric acid etching solution (FIG. 5(b)). ).
第２の絶縁膜９をＰ型半導体基板１及び第１の多結晶シ
リコン膜１１を酸化することにより形成する（第５図（
Ｃ））。第２の多結晶シリコン膜１２を堆積させ、上述
した第１の多結晶シリコン膜１１の場合と同様にして、
写真食刻法及びプラズマエツチング法によりパターニン
グして形成する（第５図（ｄ））。しかる後、層間酸化
硅素膜１５を常圧ＣＶＤ法にて形成し、アルミニウム配
線１６及び保護酸化硅素膜１７を施して第３図、第４図
の固体撮像素子を得る。A second insulating film 9 is formed by oxidizing the P-type semiconductor substrate 1 and the first polycrystalline silicon film 11 (see FIG.
C)). A second polycrystalline silicon film 12 is deposited in the same manner as in the case of the first polycrystalline silicon film 11 described above.
It is formed by patterning by photolithography and plasma etching (FIG. 5(d)). Thereafter, an interlayer silicon oxide film 15 is formed by atmospheric pressure CVD, and aluminum wiring 16 and a protective silicon oxide film 17 are applied to obtain the solid-state imaging device shown in FIGS. 3 and 4.
上述した従来の固体撮像素子は第１の多結晶シリコン膜
１１をパターニングし第１のゲート絶縁膜８をＰ型半導
体基板１表面までエツチングした後、Ｐ型半導体基板１
及び第１の多結晶シリコン膜１１を熱酸化し、第２のゲ
ート絶縁膜９を形成しているため、第２のゲート絶縁膜
９形成時に第１の多結晶シリコン膜１１及びＰ型半導体
基板１の裏面から飛び出した（アウトデイフュージョン
）りんが、基板表面の光電変換部２或は電荷転送部３の
Ｎ型層６に付着し、局部的にＮ＋層を形成する為、光電
変換部２に付着した場合には再生画面上点欠陥を生じ、
電荷転送部３のＮ型層６に付着した場合には、付着した
地点の濃度は他の地点より濃いＮ＋層を形成する為その
点の表面電位は、深くなり転送されて来た電荷はその地
点で一部トラップされる形となり、電荷の転送損失をも
たらすという欠点があった。The above-described conventional solid-state image sensor is constructed by patterning the first polycrystalline silicon film 11 and etching the first gate insulating film 8 down to the surface of the P-type semiconductor substrate 1.
Since the second gate insulating film 9 is formed by thermally oxidizing the first polycrystalline silicon film 11, the first polycrystalline silicon film 11 and the P-type semiconductor substrate are removed when the second gate insulating film 9 is formed. Phosphorus ejected from the back surface of the substrate (out-diffusion) adheres to the N-type layer 6 of the photoelectric conversion section 2 or charge transfer section 3 on the surface of the substrate, forming an N+ layer locally. If it adheres to the screen, it will cause defects on the top of the playback screen.
When it adheres to the N-type layer 6 of the charge transfer section 3, the concentration at the point where it adheres forms an N+ layer that is higher than other points, so the surface potential at that point becomes deeper and the transferred charges are This has the disadvantage that it becomes partially trapped at certain points, resulting in charge transfer loss.
本発明の固体撮像素子の製造方法は、第１の導電型の半
導体基板の一主面にそれぞれ設けられた第２導電型領域
の光電変換部と、第１のゲート絶縁膜と第１の多結晶シ
リコン電極とプラズマＣｖＤ法で形成した酸化硅素膜或
は窒化硅素膜を熱酸化した第２のゲート絶縁膜と、第２
の多結晶シリコン電極及び第２導電型領域から成る電荷
転送部と、前記光電変換部から前記電荷転送部への電荷
転送を行うトランスファゲートと前記各領域を電気的に
分離する高濃度の第１導電型のチャンネルストップ領域
を有した固体撮像素子の製造方法で、第１の多結晶シリ
コン膜をパターニングし第１のゲート絶縁膜をＰ型半導
体基板表面までエツチングした後プラズマＣＶＤ法によ
り酸化硅素膜或は窒化硅素膜を堆積し、熱酸化を行った
第２のゲート絶縁膜を形成することにより、熱工程にお
いて第１の多結晶シリコン膜及びＰ型半導体基板の裏面
からアウトデイフュージョンしたりんが前記Ｐ型半導体
表面に付着することを防ぐことが出きる。A method for manufacturing a solid-state image sensor according to the present invention includes a photoelectric conversion section of a second conductivity type region provided on one main surface of a semiconductor substrate of a first conductivity type, a first gate insulating film, and a first multilayer film. a crystalline silicon electrode, a second gate insulating film formed by thermally oxidizing a silicon oxide film or a silicon nitride film formed by a plasma CVD method;
a charge transfer section consisting of a polycrystalline silicon electrode and a second conductivity type region, a transfer gate for transferring charge from the photoelectric conversion section to the charge transfer section, and a highly concentrated first conductivity type region for electrically separating the respective regions. In a method of manufacturing a solid-state image sensor having a conductivity type channel stop region, a first polycrystalline silicon film is patterned, a first gate insulating film is etched to the surface of a P-type semiconductor substrate, and then a silicon oxide film is formed by a plasma CVD method. Alternatively, by forming a second gate insulating film by depositing a silicon nitride film and performing thermal oxidation, phosphorus out-diffused from the back surface of the first polycrystalline silicon film and the P-type semiconductor substrate during the thermal process can be removed. Adhesion to the surface of the P-type semiconductor can be prevented.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の主な製造工程における電荷
転送部の断面図である。FIG. 1 is a sectional view of a charge transfer section in the main manufacturing process of an embodiment of the present invention.
Ｐ型半導体基板１内に選択的に光電変換部２と電荷転送
部３の埋込チャンネルとなるＮ型層６及びチャンネルス
トップ５となる高濃度のＰ型層７を形成した後Ｐ型半導
体基板１を酸化して第１のゲート絶縁膜８を形成し、第
１の多結晶シリコン膜１１を堆積させ、第１の多結晶シ
リコン１１の比抵抗を下げる為及びＰ型半導体基板１の
裏面に高濃度のりんを入れて結晶欠陥を裏面に意図的に
発生させゲッタリングを行う為に前記第１の多結晶シリ
コン膜１１にりんを拡散する（第１図（ａ））。After selectively forming in the P-type semiconductor substrate 1 an N-type layer 6 that will become a buried channel for the photoelectric conversion section 2 and the charge transfer section 3 and a high concentration P-type layer 7 that will become a channel stop 5, the P-type semiconductor substrate 1 is oxidized to form a first gate insulating film 8, and a first polycrystalline silicon film 11 is deposited to lower the specific resistance of the first polycrystalline silicon 11 and on the back surface of the P-type semiconductor substrate 1. Phosphorus is diffused into the first polycrystalline silicon film 11 in order to intentionally generate crystal defects on the back surface and perform gettering by introducing a high concentration of phosphorus (FIG. 1(a)).
次に写真食刻法及びプラズマエツチング法により、第１
の多結晶シリコン膜１１をパターニングし前記第１のゲ
ート絶縁膜８をフッ酸系エツチング液にて基板表面まで
エツチングする（第１図（ｂ））。Next, by photolithography and plasma etching, the first
The polycrystalline silicon film 11 is patterned, and the first gate insulating film 8 is etched to the substrate surface using a hydrofluoric acid etching solution (FIG. 1(b)).
プラズマＣＶＤ法を用いて酸化硅素膜１３を約１０ｎｍ
から５０ｎｍ堆積させる（第１ （ｃ）図）。Silicon oxide film 13 is approximately 10 nm thick using plasma CVD method.
(FIG. 1(c)).
プラズマＣＶＤ法にて堆積させた酸化硅素膜１３に熱酸
化を施し第２のゲート絶縁膜９を形成する（第１図（ｄ
））。The silicon oxide film 13 deposited by plasma CVD is thermally oxidized to form a second gate insulating film 9 (see FIG. 1(d)).
)).
第２の多結晶シリコン膜１２を堆積させ上述した第１の
多結晶シリコン膜１１の場合と同様にして写真食刻法及
びプラズマエツチング法によりパターニングする（第１
図（ｅ））。A second polycrystalline silicon film 12 is deposited and patterned by photolithography and plasma etching in the same manner as in the case of the first polycrystalline silicon film 11 described above.
Figure (e)).
しかる後、層間酸化膜層を常圧ＣＶＤ法にて形成しアル
ミニウム配線及び保護酸化膜を施して固体撮像素子を得
る。Thereafter, an interlayer oxide film layer is formed by atmospheric pressure CVD, and aluminum wiring and a protective oxide film are applied to obtain a solid-state image sensor.
第２図は本発明の他の実施例の主な製造工程における電
荷転送部の断面図である。FIG. 2 is a sectional view of a charge transfer section in the main manufacturing process of another embodiment of the present invention.
第２図（Ｃ）においてプラズマＣＶＤ法において窒化硅
素膜１４を約１０ｎｍから３０ｎｍ堆積させている以外
は第１図に示した実施例と同一である。The embodiment is the same as the embodiment shown in FIG. 1, except that in FIG. 2(C), a silicon nitride film 14 is deposited to a thickness of approximately 10 nm to 30 nm using the plasma CVD method.
第２図（ｅ）において第２の多結晶シリコン膜１２のパ
ターニング終了後、層間酸化膜層を常圧ＣＶＤ法にて形
成し、アルミニウム配線及び保護酸化膜を施して固体撮
像素子を得る。In FIG. 2(e), after patterning the second polycrystalline silicon film 12, an interlayer oxide film layer is formed by atmospheric pressure CVD, and aluminum wiring and a protective oxide film are applied to obtain a solid-state image sensor.
以上説明した様に、本発明によれば固体撮像素子の製造
工程において、第２のゲート絶縁膜をプラズマＣＶＤ法
で形成した酸化硅素膜或は窒化硅素膜を熱酸化し、形成
することにより、第２のゲート絶縁膜形成時に第１の多
結晶シリコン膜及びＰ型半導体基板の裏面からアウトデ
イフュージョンしたりんが基板表面の光電変換部或は電
荷転送部のＮ型層に付着し、局部的なＮ＋層を形成する
のを抑制することが出来、テレビジョンカメラシステム
として使用した場合前記局部的なＮ＋層に起因する再生
画面上の点欠陥及び電荷の転送損傷による棒状欠陥を抑
制することが出来るという効果がある。As explained above, according to the present invention, in the manufacturing process of a solid-state image sensor, the second gate insulating film is formed by thermally oxidizing a silicon oxide film or a silicon nitride film formed by a plasma CVD method. During the formation of the second gate insulating film, phosphorus outdiffused from the first polycrystalline silicon film and the back surface of the P-type semiconductor substrate adheres to the N-type layer of the photoelectric conversion section or charge transfer section on the substrate surface, causing local damage. When used as a television camera system, point defects on the playback screen caused by the localized N+ layer and rod-like defects due to charge transfer damage can be suppressed. There is an effect that it can be done.
（ｅ）は本発明の他の実施例の主な製造工程における電
荷転送部の断面図である。
第３図は従来技術の一例である２層多結晶シリコン電極
構造の電荷結合素子を用いた固体撮像素子の平面図、第
４図（ａ）は第３図Ｉ−１’面の断面図、第４図（ｂ）
は第３図ｎ−ｎ’面の断面図、第５図は従来の固体撮像
素子の主な製造工程における電荷転送部の断面図である
。
１・・・・・・Ｐ型半導体基板、２・・・・・・光電変
換部、３・・・・・・電荷転送部、４・・・・・・トラ
ンスファゲート部、５・・・・・・チャンネルストップ
、６・・・・・・Ｎ型層、７・・・・・・Ｐ型層、８・
・・・・・第１のゲート絶縁膜、９・・・・・・第２ゲ
ート絶縁膜、１０・・・・・・ゲート絶縁膜、１１・・
・・・・第１の多結晶シリコン膜、１２・・・・・・第
２の多結晶シリコン膜、１３・・・・・・プラズマＣＶ
Ｄ酸化硅素膜、１４・・・・・・プラズマＣＶＤ窒化硅
素膜、１５・・・・・・常圧ＣＶＤ層間酸化硅素膜、１
６・・・・・・アルミニウム配線、１７・・・・・・保
護酸化硅素膜。
代理人 弁理士 内 原 晋
窟１図（し）
肩１図（の
第１回（め
７７Ｍ１め９′米吉晶シリ］〕万吟
７扁ｚ図（（Ｌ）
／／
第１圓（脚
りｒデ２−Ｌン■ｔｏ４ノ
片３図
／２．ｊ１５２ｆ）ｚダｔ４ｈ閣ｉシリＬ１５に！し冒
刀（Ｃ）
′！Ｊ４図ｒ幻
菊４図Ｃらジ
第５図（７１）
筋５図（＃））
刻５回（ｄ）(e) is a cross-sectional view of the charge transfer section in the main manufacturing process of another embodiment of the present invention. FIG. 3 is a plan view of a solid-state imaging device using a charge-coupled device with a two-layer polycrystalline silicon electrode structure, which is an example of the conventional technology, and FIG. 4(a) is a cross-sectional view taken along plane I-1' in FIG. Figure 4(b)
3 is a cross-sectional view taken along line nn' in FIG. 3, and FIG. 5 is a cross-sectional view of a charge transfer section in the main manufacturing process of a conventional solid-state image sensor. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Photoelectric conversion section, 3... Charge transfer section, 4... Transfer gate section, 5... ...Channel stop, 6...N type layer, 7...P type layer, 8...
...First gate insulating film, 9... Second gate insulating film, 10... Gate insulating film, 11...
...First polycrystalline silicon film, 12... Second polycrystalline silicon film, 13... Plasma CV
D silicon oxide film, 14... plasma CVD silicon nitride film, 15... normal pressure CVD interlayer silicon oxide film, 1
6... Aluminum wiring, 17... Protective silicon oxide film. Agent Patent Attorney Shinku Uchihara 1st drawing (shi) Shoulder 1st drawing (1st (Me77M1me9' Akira Yoneyoshi)) Mangin 7th z drawing ((L) // 1st round (legs) r de 2-L n ■to4 no piece 3 figure/2.j152f) z da t4h cabinet i Shiri L15!Shi Sword (C) '!J4 figure r Genkiku 4 figure C raji figure 5 (71) 5 lines (#)) 5 times (d)
Claims (1)
れた第２導電型領域の光電変換部と、第１のゲート絶縁
膜と第１の多結晶シリコン電極と第２のゲート絶縁膜と
第２の多結晶シリコン電極及び第２導電型領域から成る
電荷転送部と、前記光電変換部から前記電荷転送部への
電荷転送を行うトランスファゲートと、前記各領域を電
気的に分離する高濃度の第１導電型のチャンネルストッ
プ領域とを有する固体撮像素子の製造方法において、前
記第２のゲート絶縁膜がプラズマＣＶＤ法で形成した硅
素の絶縁物膜を熱酸化して形成されることを特徴とする
固体撮像素子の製造方法 ２、前記硅素の絶縁物膜は酸化硅素膜である請求項１記
載の固体撮像素子の製造方法 ３、前記硅素の絶縁物膜は窒化硅素膜である請求項１記
載の固体撮像素子の製造方法[Claims] 1. A photoelectric conversion section of a second conductivity type region provided on one main surface of a semiconductor substrate of a first conductivity type, a first gate insulating film, and a first polycrystalline silicon electrode. a charge transfer section including a second gate insulating film, a second polycrystalline silicon electrode, and a second conductivity type region; a transfer gate that transfers charge from the photoelectric conversion section to the charge transfer section; In the method for manufacturing a solid-state imaging device having a highly concentrated first conductivity type channel stop region that is electrically isolated, the second gate insulating film is formed by thermally oxidizing a silicon insulating film formed by a plasma CVD method. 2. A method 3 for manufacturing a solid-state image sensor according to claim 1, wherein the silicon insulator film is a silicon oxide film. The silicon insulator film is a nitride film. The method for manufacturing a solid-state imaging device according to claim 1, which is a silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63237707A JP3036747B2 (en) | 1988-09-21 | 1988-09-21 | Method for manufacturing solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63237707A JP3036747B2 (en) | 1988-09-21 | 1988-09-21 | Method for manufacturing solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0284768A true JPH0284768A (en) | 1990-03-26 |
| JP3036747B2 JP3036747B2 (en) | 2000-04-24 |
Family
ID=17019313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63237707A Expired - Lifetime JP3036747B2 (en) | 1988-09-21 | 1988-09-21 | Method for manufacturing solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036747B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100269549B1 (en) * | 1996-04-19 | 2000-10-16 | 가네꼬 히사시 | Two phase clock type charge coupled device having electrodes with side walls and method for producing the same |
| CN103400847A (en) * | 2013-08-14 | 2013-11-20 | 中国电子科技集团公司第四十四研究所 | Technology for manufacturing CCD secondary or more than secondary polycrystalline silicon |
| CN109256441A (en) * | 2018-09-20 | 2019-01-22 | 北方电子研究院安徽有限公司 | A kind of EMCCD device mul-tiple layers of polysilicon grid structure production method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5448484A (en) * | 1977-08-30 | 1979-04-17 | Toshiba Corp | Forming method of insulation film |
| JPS5851673A (en) * | 1981-09-22 | 1983-03-26 | Sharp Corp | solid state imaging device |
| JPS60263437A (en) * | 1984-06-12 | 1985-12-26 | Ise Electronics Corp | Manufacturing method of thin film transistor |
| JPS61156885A (en) * | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Polycrystalline semiconductor device and manufacture thereof |
| JPS61214463A (en) * | 1985-03-19 | 1986-09-24 | Nec Corp | Solid-state imaging device and its driving method |
-
1988
- 1988-09-21 JP JP63237707A patent/JP3036747B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5448484A (en) * | 1977-08-30 | 1979-04-17 | Toshiba Corp | Forming method of insulation film |
| JPS5851673A (en) * | 1981-09-22 | 1983-03-26 | Sharp Corp | solid state imaging device |
| JPS60263437A (en) * | 1984-06-12 | 1985-12-26 | Ise Electronics Corp | Manufacturing method of thin film transistor |
| JPS61156885A (en) * | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Polycrystalline semiconductor device and manufacture thereof |
| JPS61214463A (en) * | 1985-03-19 | 1986-09-24 | Nec Corp | Solid-state imaging device and its driving method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100269549B1 (en) * | 1996-04-19 | 2000-10-16 | 가네꼬 히사시 | Two phase clock type charge coupled device having electrodes with side walls and method for producing the same |
| CN103400847A (en) * | 2013-08-14 | 2013-11-20 | 中国电子科技集团公司第四十四研究所 | Technology for manufacturing CCD secondary or more than secondary polycrystalline silicon |
| CN109256441A (en) * | 2018-09-20 | 2019-01-22 | 北方电子研究院安徽有限公司 | A kind of EMCCD device mul-tiple layers of polysilicon grid structure production method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3036747B2 (en) | 2000-04-24 |
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