JPH0284795A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH0284795A JPH0284795A JP63237144A JP23714488A JPH0284795A JP H0284795 A JPH0284795 A JP H0284795A JP 63237144 A JP63237144 A JP 63237144A JP 23714488 A JP23714488 A JP 23714488A JP H0284795 A JPH0284795 A JP H0284795A
- Authority
- JP
- Japan
- Prior art keywords
- protective glass
- integrated circuit
- circuit device
- glass
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は、多層構造を成した集積回路装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device having a multilayer structure.
[従来技術]
従来、混成集積回路装置(ハイブリッドIC)の小型・
軽団化のために厚膜多周構造が採用されている。これは
、第3図に示すように、アルミナ基板1上に厚膜回路(
導体)2を形成し、この上に層間絶縁材料としての結晶
質あるいは非晶質より成るガラス3を形成し、その上に
導体4.抵抗体5を形成し、保護ガラス(はうけい酸鉛
を主成分とする非結晶系ガラス)6にてその表面を保護
している。尚、第3図おいては、ピアホール7により層
間(導体2,4間〉を電気接続するとともに、導体4上
に半導体チップ8を配置している。[Prior art] Conventionally, hybrid integrated circuit devices (hybrid ICs) have been made smaller and smaller.
A thick film multi-circle structure has been adopted to make it lighter. As shown in FIG. 3, this thick film circuit (
A conductor) 2 is formed thereon, a crystalline or amorphous glass 3 as an interlayer insulating material is formed thereon, and a conductor 4. A resistor 5 is formed, and its surface is protected with a protective glass 6 (amorphous glass containing lead silicate as a main component). In FIG. 3, a peer hole 7 is used to electrically connect the layers (between the conductors 2 and 4), and a semiconductor chip 8 is placed on the conductor 4.
[発明が解決しようとする課題]
ところが、第3図中にカッコ内に示したように各材料の
熱膨張係数が異なり、アルミナ基板1よりその熱膨張係
数が小さな結晶化ガラス3が基板全面に形成されている
ので、両部材1.3による熱膨張係数と保護ガラス6の
熱膨張係数との差により保護ガラス6の焼成時の冷却工
程で保護ガラス6に引張り応力が強く働くことになる。[Problem to be solved by the invention] However, as shown in parentheses in FIG. Therefore, due to the difference between the coefficient of thermal expansion of both members 1.3 and the coefficient of thermal expansion of the protective glass 6, a strong tensile stress acts on the protective glass 6 during the cooling process during firing of the protective glass 6.
この応力により第4図に示すように導体4と抵抗体5の
境界付近における保護ガラス6の表面にクラックCが発
生する。このクラックCが抵抗体5内部にまで進行する
と抵抗体5の抵抗値が変化してしまうという問題があっ
た。This stress causes cracks C to occur on the surface of the protective glass 6 near the boundary between the conductor 4 and the resistor 5, as shown in FIG. When this crack C progresses to the inside of the resistor 5, there is a problem in that the resistance value of the resistor 5 changes.
このとき、保護ガラス6の熱膨張係数を層間絶縁層とし
てのガラス3の熱膨張係数に近づけるだけではクラック
を防止できない。At this time, cracks cannot be prevented simply by bringing the thermal expansion coefficient of the protective glass 6 closer to the thermal expansion coefficient of the glass 3 serving as the interlayer insulating layer.
この発明の目的は、多層@造を成す集積回路装置におい
てその材料の熱膨張係数に基因する保護ガラスのクラッ
クの発生を抑制し信頼性の高い集積回路装置を提供する
ことにある。An object of the present invention is to provide a highly reliable integrated circuit device that suppresses the occurrence of cracks in a protective glass caused by the coefficient of thermal expansion of the material in an integrated circuit device having a multilayer structure.
[課題を解決するための手段]
この発明は、基板上に導体と絶縁材料を積層して多層構
造とし、その表面を保護ガラスにて覆うようにした集積
回路装置において、前記保護ガラス中に混入物を分散さ
けた集積回路装置をその要旨とする。[Means for Solving the Problems] The present invention provides an integrated circuit device in which a conductor and an insulating material are laminated on a substrate to form a multilayer structure, and the surface of the integrated circuit device is covered with a protective glass. Its gist is an integrated circuit device that avoids dispersing objects.
[作用]
各材料の熱膨張係数に基因して保護ガラスに応力が加わ
るが、保護ガラス中に分散させた混入物がクラックの進
行を阻止する。[Function] Although stress is applied to the protective glass due to the coefficient of thermal expansion of each material, the contaminants dispersed in the protective glass prevent the progression of cracks.
[実施例コ
この発明を具体化した一実施例を図面に従って説明する
。[Embodiment] An embodiment embodying the present invention will be described with reference to the drawings.
本実施例の混成集積回路装置は、前記第3図に示したも
のに比べ、第1図に示すように前記保護ガラス(非結晶
系ガラス)6に混入物としてのセラミックフィラー又は
結晶質ガラス9を分散させた部分のみ異なっており、他
の部分は第3図に示したものと同じである。The hybrid integrated circuit device of this embodiment is different from that shown in FIG. 3, as shown in FIG. 1, as shown in FIG. The only difference is the portion where the rays are dispersed, and the other portions are the same as shown in FIG.
第2図にはその実験結果を示し、第2図の横軸は保護ガ
ラス6の熱膨張係数(混入物9を分散ざぜた場合はみか
け上の熱膨張係数)を、縦軸には抵抗体5の保護ガラス
6の焼成前後での抵抗値の変化を示す。その第2図にお
いて、プロット点Aは、熱膨張係数が8.1Dpm/”
Cの保護ガラス6に何も分散させない場合を示す。Figure 2 shows the experimental results. 5 shows the change in resistance value of the protective glass 6 of No. 5 before and after firing. In Figure 2, plot point A has a thermal expansion coefficient of 8.1 Dpm/''
A case in which nothing is dispersed on the protective glass 6 of C is shown.
これに対し、プロワ1〜点B、C,Dは、熱膨張係数が
8.’lpm/’Cの保冷ガラス6にセラミックフィラ
ーを分散させた場合を示す。この場合のセラミックフィ
ラーは、成分が酸化ジルコニアで、粒子径が0.5〜2
μmに成形したものを使用している。この酸化ジルコニ
アは、保護ガラス(非結晶系ガラス)6の成分の一つで
ある鉛酸化物と製品の製造温度である5 00 ’C付
近でも化学的な反応をしない。On the other hand, blower 1 to points B, C, and D have a thermal expansion coefficient of 8. A case is shown in which ceramic filler is dispersed in cold glass 6 of 'lpm/'C. The ceramic filler in this case is composed of zirconia oxide and has a particle size of 0.5 to 2.
We use products molded to micrometers. This zirconia oxide does not chemically react with lead oxide, which is one of the components of the protective glass (non-crystalline glass) 6, even at around 500'C, which is the manufacturing temperature of the product.
又、プロット点Eは、保護ガラス6の一部の組成を変更
することによって結晶させた場合を示す。Moreover, plot point E shows the case where the protective glass 6 is crystallized by changing the composition of a part thereof.
この結晶化ガラスの径は0.5〜2μmである。The diameter of this crystallized glass is 0.5 to 2 μm.
この第2図から明らかなように、保護ガラス6に何も分
散させない場合(プロット点A)に比べ保護ガラス6に
レラミックフィラーの分散あるいはガラスの一部を結晶
化ガラスとすることによって(プロプ1へ点B−E)、
保護ガラス6のみかけ上の熱膨張係数を低下させること
ができるとともに、抵ル体5の抵抗値変化を少なく゛す
ることができる。As is clear from FIG. 2, compared to the case where nothing is dispersed in the protective glass 6 (plot point A), by dispersing Relamic filler in the protective glass 6 or making a part of the glass crystallized glass (prop. 1 to point B-E),
The apparent coefficient of thermal expansion of the protective glass 6 can be lowered, and changes in the resistance value of the resistor 5 can be reduced.
この現象を考察してみると、保護ガラス6のみかけ上の
熱膨張係数を低下させることができるために材料の熱膨
張係数に基因する保護ガラス6への引張り応力を減少も
しくはガラスの有する強い耐圧縮応力特性のためクラッ
クCの発生を抑11i1 u抵抗体5の抵抗値変化を減
少させることができる。Considering this phenomenon, it is possible to reduce the apparent thermal expansion coefficient of the protective glass 6, thereby reducing the tensile stress on the protective glass 6 caused by the thermal expansion coefficient of the material, or the strong resistance of the glass. Because of the compressive stress characteristics, the occurrence of cracks C can be suppressed and changes in the resistance value of the resistor 5 can be reduced.
又、第1図に示すように、保護ガラス6の表面でクラッ
クCの核が発生しても、セラミックフィラー又は結晶化
ガラスによりその進行が抑制されそれ以上クラックCが
広がらず抵抗体5にまで至らないと考えられる。Furthermore, as shown in FIG. 1, even if a crack C nucleus occurs on the surface of the protective glass 6, its progression is suppressed by the ceramic filler or crystallized glass, and the crack C does not spread any further and reaches the resistor 5. It is considered that this will not be possible.
このように本実施例においては、保護ガラス6の表面で
クラックCの核が発生しても、セラミックフィラー又は
結晶化ガラスによりその進行が抑制され、その材料の熱
膨張係数に基因する保護ガラスのクラックの発生を抑制
し信頼性の高いものとすることができる。As described above, in this embodiment, even if a crack C nucleus occurs on the surface of the protective glass 6, its progress is suppressed by the ceramic filler or crystallized glass, and the growth of the protective glass due to the thermal expansion coefficient of the material is suppressed. The occurrence of cracks can be suppressed and reliability can be improved.
この発明は上記実施例に限定されることなく、保護ガラ
ス6中に分散させる混入物としては、酸化ジルコニアの
他のセラミックフィラーを使用したり、気泡を分散させ
てもよい。The present invention is not limited to the above-mentioned embodiments, and as a contaminant to be dispersed in the protective glass 6, a ceramic filler other than zirconia oxide may be used, or air bubbles may be dispersed.
[発明の効果]
以上詳述したようにこの発明によれば、多層構造を成す
集積回路装置においてその材料の熱膨張係数に基因する
保護ガラスのクランクの発生を抑制し信頼性の高いもの
とすることができる優れた効果を発揮する。[Effects of the Invention] As detailed above, according to the present invention, it is possible to suppress the occurrence of cranking of the protective glass due to the coefficient of thermal expansion of the material in an integrated circuit device having a multilayer structure, thereby making the device highly reliable. Demonstrates excellent effects that can be achieved.
第1図は実施例の混成集積回路装置における保護ガラス
の断面図、第2図は実験結果を示す図、第3図は混成集
積回路装置の断面図、第4図は従来技術を説明するため
の混成集積回路装置の断面図である。
1はアルミナ基板、2は厚膜回路(導体)、3は結晶質
あるいは非晶質より成るガラス、4は導体、6は保護ガ
ラス、9は混入物。
特許出願人 日本電装 株式会社代 理 人
弁理士 恩1)博宣第1図
第4図
熱伺久椋改(ρ門A)Fig. 1 is a cross-sectional view of the protective glass in the hybrid integrated circuit device of the example, Fig. 2 is a view showing the experimental results, Fig. 3 is a cross-sectional view of the hybrid integrated circuit device, and Fig. 4 is for explaining the prior art. 1 is a sectional view of a hybrid integrated circuit device of FIG. 1 is an alumina substrate, 2 is a thick film circuit (conductor), 3 is crystalline or amorphous glass, 4 is a conductor, 6 is protective glass, and 9 is a contaminant. Patent applicant Nippondenso Co., Ltd. Agent
Patent Attorney On 1) Hironobu Figure 1 Figure 4 Netsuki Hisagura Kai (ρmon A)
Claims (1)
その表面を保護ガラスにて覆うようにした集積回路装置
において、 前記保護ガラス中に混入物を分散させたことを特徴とす
る集積回路装置。1. A multilayer structure is created by laminating conductors and insulating materials on a substrate.
1. An integrated circuit device whose surface is covered with a protective glass, characterized in that contaminants are dispersed in the protective glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63237144A JPH07101774B2 (en) | 1988-09-21 | 1988-09-21 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63237144A JPH07101774B2 (en) | 1988-09-21 | 1988-09-21 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0284795A true JPH0284795A (en) | 1990-03-26 |
| JPH07101774B2 JPH07101774B2 (en) | 1995-11-01 |
Family
ID=17011059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63237144A Expired - Lifetime JPH07101774B2 (en) | 1988-09-21 | 1988-09-21 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101774B2 (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5337856A (en) * | 1976-09-20 | 1978-04-07 | Hitachi Ltd | Thick film circuit and method of producing same |
| JPS5482700A (en) * | 1977-12-15 | 1979-07-02 | Nec Corp | Paste compound for insulator forming |
| JPS55111152A (en) * | 1979-02-21 | 1980-08-27 | Hitachi Ltd | Method of manufacturing multilayer thin film circuit board |
| JPS55113641A (en) * | 1979-02-22 | 1980-09-02 | Asahi Glass Co Ltd | Insulating glass composition |
| JPS5734046A (en) * | 1980-07-29 | 1982-02-24 | Asahi Glass Co Ltd | Dielectric glass composition |
| JPS5817695A (en) * | 1981-07-24 | 1983-02-01 | 株式会社日立製作所 | Multilayer circuit board and method of producing same |
| JPS59193096A (en) * | 1983-04-16 | 1984-11-01 | 株式会社日立製作所 | Thick film hybrid integrated circuit board |
| JPS6150395A (en) * | 1984-08-20 | 1986-03-12 | 日立化成工業株式会社 | Method of producing ceramic multilayer circuit board |
| JPS6265956A (en) * | 1985-09-18 | 1987-03-25 | Fujitsu Ltd | Production of glass ceramic insulating paste |
-
1988
- 1988-09-21 JP JP63237144A patent/JPH07101774B2/en not_active Expired - Lifetime
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5337856A (en) * | 1976-09-20 | 1978-04-07 | Hitachi Ltd | Thick film circuit and method of producing same |
| JPS5482700A (en) * | 1977-12-15 | 1979-07-02 | Nec Corp | Paste compound for insulator forming |
| JPS55111152A (en) * | 1979-02-21 | 1980-08-27 | Hitachi Ltd | Method of manufacturing multilayer thin film circuit board |
| JPS55113641A (en) * | 1979-02-22 | 1980-09-02 | Asahi Glass Co Ltd | Insulating glass composition |
| JPS5734046A (en) * | 1980-07-29 | 1982-02-24 | Asahi Glass Co Ltd | Dielectric glass composition |
| JPS5817695A (en) * | 1981-07-24 | 1983-02-01 | 株式会社日立製作所 | Multilayer circuit board and method of producing same |
| JPS59193096A (en) * | 1983-04-16 | 1984-11-01 | 株式会社日立製作所 | Thick film hybrid integrated circuit board |
| JPS6150395A (en) * | 1984-08-20 | 1986-03-12 | 日立化成工業株式会社 | Method of producing ceramic multilayer circuit board |
| JPS6265956A (en) * | 1985-09-18 | 1987-03-25 | Fujitsu Ltd | Production of glass ceramic insulating paste |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07101774B2 (en) | 1995-11-01 |
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Legal Events
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|---|---|---|---|
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| EXPY | Cancellation because of completion of term |