JPH0284833A - Digital signal synchronization supervisory circuit - Google Patents

Abstract

PURPOSE:To accelerate the supervision of frame synchronization by providing a shift register of (n) stages and a frame synchronization supervisory circuit which performs collation with a synchronous pattern of (n) bits whose entire parallel output to the shift register are decided. CONSTITUTION:The frame synchronization supervisory circuit 5 is provided at the synchronization supervisory part of a digital signal in which (n) bits are synchronously multiplexed as information unit and also, the synchronous patterns of (n) bits are arranged concentrically. Then, the digital signal 1 that is (n) bit information unit is outputted to the shift register 4 of (n) stages. The register 4 inputs the signal 1, and outputs signals S1, S2...Sn being shifted by every bit to the circuit 5. The circuit 5 performs the collation with the synchronous pattern of (n) bits whose entire parallel output to the register 4 are decided. In other words, as for the signals (S1-Sn), frame synchronization patterns appear in parallel, then, detection is performed. In such a way, it is possible to perform the supervision of the frame synchronization at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to synchronization monitoring of digital signals synchronously multiplexed using a plurality of bits as information units, and more particularly to a frame synchronization monitoring circuit.

Conventional technology Conventionally, this type of digital signal synchronization monitoring circuit.

The configuration was as shown in Figure 2.

In FIG. 2, a digital signal 7 whose information unit is n bits is converted into l:n serially and /'parallelly m (S/P conversion) in a serial/parallel conversion circuit (S/P) 12. , the data is stored in units of 1 bit. Then, the frame synchronization pattern therein is inputted to the frame synchronization monitoring circuit 13 to check the frames and monitor the synchronization.

In this case, as shown in FIG. 4, in serial/parallel conversion, the frame synchronization patterns are not always arranged in parallel, so the serial/parallel conversion circuit 12
control is necessary.

Problems to be Solved by the Invention The conventional digital signal synchronization monitoring circuit described above is
Since the frame synchronization patterns are not always arranged in parallel during parallel conversion, it is necessary to constantly control the serial/parallel conversion circuit, and the disadvantage is that it takes a long time until the frame synchronization patterns are arranged in a normal order. There is.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel digital signal synchronization monitoring circuit which makes it possible to eliminate the above-mentioned drawbacks inherent in the prior art.

Means for Solving the Problems In order to achieve the above objects, a digital signal synchronization monitoring circuit according to the present invention is configured to monitor a digital signal that is synchronously multiplexed using n bits as an information unit and in which a synchronization pattern of n bits is centrally arranged. In the synchronization monitoring unit of the n-stage shift register and all parallel outputs of the shift register are
It is configured to include a frame synchronization monitoring circuit that checks the bit synchronization pattern.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to Figure 1, 1 is a digital signal whose information unit is n bits, 2 is a clock, 3 is a signal equivalent to signal 1, 4 is a 0-stage shift register, 5 is a frame synchronization monitoring circuit, and 6 is a frame. Each pulse is shown, and S1 to Sn are 1
This signal is equivalent to digital signal 1 whose information unit is n bits shifted bit by bit.

In FIG. 1, a digital signal 1, which is a unit of n bit information, is input to an n-stage shift register 4, and signals 81 to Sn shifted one bit at a time are input to a frame synchronization monitoring circuit 5, and frame configuration information bits are input to a frame synchronization monitoring circuit 5. Perform n matches. In this case, the relationship between the signals 81 to Sn is as shown in FIG. 3, and frame synchronization patterns appear in parallel and are detected.

As described in detail, according to the present invention, by inputting a signal shifted by a shift register to a frame monitoring circuit, frame synchronization can be monitored at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the digital signal synchronization monitoring circuit according to the present invention, FIG. 2 is a block diagram of a conventional digital signal synchronization monitoring circuit, and FIG. 3 is the circuit shown in FIG. 1. Timing chart of operation (n=
4), FIG. 4 is an operation timing chart (n; 4) of the circuit shown in FIG. 1.7...Digital signal whose information unit is n bits, 2,8...Clock, 3...Signal equivalent to signal l, 4...0-stage shift register, 5...Frame synchronization Monitoring circuit, 6.11... frame pulse, 81~Sn
...Signal equivalent to signal l shifted by 1 bit, 9
...2.8! frequency clock, lO...control signal for circuit 12, 12...serial/parallel conversion circuit, 1
3... Frame synchronization monitoring circuit, 14... Minute period (1
8), P1 to Pn... Parallel expanded signals of signal 7 Figure 1 Patent applicant Agent of NEC Corporation

Claims (1)

[Claims] In a digital signal synchronization monitoring section in which n bits are synchronously multiplexed as information units and n-bit synchronization patterns are centrally arranged, there is an n-stage shift register and n bits whose all parallel outputs of the shift register are determined. 1. A digital signal synchronization monitoring circuit comprising: a frame synchronization monitoring circuit that performs matching with a synchronization pattern of the digital signal synchronization monitoring circuit.