JPH0284937U - - Google Patents
Info
- Publication number
- JPH0284937U JPH0284937U JP16284888U JP16284888U JPH0284937U JP H0284937 U JPH0284937 U JP H0284937U JP 16284888 U JP16284888 U JP 16284888U JP 16284888 U JP16284888 U JP 16284888U JP H0284937 U JPH0284937 U JP H0284937U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- signal
- computer
- interface
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第１図は本考案実施例の回路構成を示す回路図
、第２図は本考案実施例を適用したシステム構成
を示すブロツク図、第３図ないし第６図はそれぞ
れ第１図に示すリセツト回路１００のリセツト信
号発生タイミングを示すタイミングチヤートであ
る。
１：プログラマブルコントローラ、２，３：入
出力装置、４：コンピユータ、１０：デコーダ、
１１：Ｄ型フリツプフロツプ、１２：ウオツチド
ツグタイマ回路、１３：オア回路。
Fig. 1 is a circuit diagram showing the circuit configuration of the embodiment of the present invention, Fig. 2 is a block diagram showing the system configuration to which the embodiment of the invention is applied, and Figs. 3 to 6 are the reset circuits shown in Fig. 1, respectively. This is a timing chart showing the reset signal generation timing of 100. 1: Programmable controller, 2, 3: Input/output device, 4: Computer, 10: Decoder,
11: D-type flip-flop, 12: watchdog timer circuit, 13: OR circuit.
Claims (1)
コンピユータのインターフエースのリセツトを行
うリセツト回路において、前記コンピユータの内
部の演算処理回路から送出されたデータ信号を入
力し、前記データ信号がリセツトを指示する信号
または該リセツトの解除を指示する信号であるこ
とを検出して検出信号を出力する検出部と、該検
出部からの前記検出信号に応じて前記インターフ
エースのリセツトまたは該リセツトの解除の処理
を行う処理部とを具えたことを特徴とするコンピ
ユータのインターフエースのリセツト回路。 In a reset circuit that resets an interface of a computer for connection to an external processing circuit through a line, a data signal sent from an internal arithmetic processing circuit of the computer is input, and the data signal is a signal instructing reset. or a detection unit that detects that the signal is a signal instructing cancellation of the reset and outputs a detection signal, and performs processing of resetting the interface or canceling the reset in response to the detection signal from the detection unit. 1. A reset circuit for a computer interface, comprising a processing section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16284888U JPH0284937U (en) | 1988-12-15 | 1988-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16284888U JPH0284937U (en) | 1988-12-15 | 1988-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284937U true JPH0284937U (en) | 1990-07-03 |
Family
ID=31447051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16284888U Pending JPH0284937U (en) | 1988-12-15 | 1988-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284937U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5553761A (en) * | 1978-10-18 | 1980-04-19 | Nec Corp | Information processor |
-
1988
- 1988-12-15 JP JP16284888U patent/JPH0284937U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5553761A (en) * | 1978-10-18 | 1980-04-19 | Nec Corp | Information processor |
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