JPH0287553A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent any cracking and disconnection from occurring due to the step difference in an upper layer wiring provided on the second interlayer insulating film by relieving the step difference including the underneath layer of a lower layer wiring by a method wherein an interlayer conductor layer having inverted pattern to that of the lower layer wiring is provided on the first interlayer insulating film provided on the lower layer wiring. CONSTITUTION:An aluminum wiring 6 to be a lower layer wiring is formed on a silicon oxide film 5. First, another silicon oxide film 7 to be the first interlayer film is provided on the surface including the aluminum wiring 6. Secondly, an aluminum layer is deposited on the film 7 to form an intermediate conductor layer 8 by selectively etching the aluminum layer. Thirdly, the other silicon film 9 to be the second interlayer insulating film is deposited on the surface including the intermediate layer 8 to make opening parts by selectively etching the silicon oxide film 9. Lastly, another aluminum layer is deposited on the surface including the silicon oxide film 9 to form an aluminum wiring 10 to be an upper layer wiring electrically connecting to the intermediate conductor layer 8 in the opening part by selectively etching the aluminum layer. As for the mask to form the intermediate conductor layer, the mask pattern to form the aluminum wiring 6 inverted for making respective parts smaller by several mum is applicable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor device having multilayer wiring.

[Conventional technology]

Multilayer wiring is used as one of the techniques for increasing the integration density of semiconductor integrated circuits.

Figure 2 (a>, (b) is a semiconductor chip layout diagram and B-B for explaining an example of a conventional semiconductor integrated circuit.
' It is a line sectional view.

As shown in FIGS. 2(a) and (b), a P-type silicon substrate 1
A gate electrode 3 formed on the gate insulating film 2 via a gate insulating film 2, an N-type diffusion region 4 provided in the P-type silicon substrate 1 in alignment with the gate electrode 3, and a gate ring f! Set on the surface containing 3,
A thin silicon oxide film 5, an aluminum wiring 6 as a lower layer wiring provided on the silicon oxide film 5, and an aluminum wire 6
It has a silicon oxide film 7 provided on the surface including the silicon oxide film 7, and an aluminum film 10 as an upper layer wiring provided on the silicon oxide film 7.

[Problem to be solved by the invention]

In the above-mentioned conventional semiconductor integrated circuit device, when the step part of the lower layer interconnection and the step part of the underlying layer coincide, a steep step part is generated in the interlayer insulating film, and the upper layer wiring provided on the interlayer insulating film is caused to have cracks or cracks due to the step difference. There is a problem in that wire breakage occurs, reducing the reliability of the semiconductor integrated circuit. In order to alleviate such a step difference, it is necessary to design the end portion of the lower layer wiring to be separated from the step portion of the underlying layer, which poses a problem that the degree of integration cannot be increased.

Furthermore, since the surface of this semiconductor integrated circuit is covered only with an insulator, problems such as logic value fluctuations within the circuit due to alpha rays mixed in from the outside and malfunctions due to temperature rise of the resistor occur.

[Means to solve the problem]

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit having multilayer wiring, which includes a lower wiring, a first interlayer insulating film provided on a surface including the lower wiring, and a region other than the area on the lower wiring pattern. An intermediate conductor layer provided on the first interlayer insulating film, a second interlayer insulating film provided on the surface including the intermediate conductor layer, and an upper layer wiring provided on the second interlayer insulating film. Consists of.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a layout diagram and a sectional view taken along the line A-A' of a semiconductor chip for explaining one embodiment of the present invention.

As shown in FIGS. 1(a) and (b), a gate electrode 3 is selectively provided on a P-type silicon substrate 1 via a gate insulating film 2, and aligned with the gate electrode 3, the P-type silicon substrate An N-type diffusion region 4 is provided in the silicon oxide film 1. Next, a silicon oxide film 5 is deposited on the surface including the gate electrode 3, and an aluminum layer is deposited on the silicon oxide film 5, and this is selectively etched. , an aluminum wiring 6 is formed as a lower layer wiring.

Next, a silicon oxide film 7 is provided as a first interlayer insulating film on the surface including the aluminum wiring 6.

Next, an aluminum layer having approximately the same thickness as the aluminum wiring 6 is deposited on the silicon oxide film 7, and the aluminum layer on the pattern occupied by the aluminum wiring 6 is selectively etched to form an intermediate conductor layer 8. . Next, a silicon oxide film 9 is deposited as a second interlayer insulating film on the surface including the intermediate conductor layer 8, and a silicon oxide film 9 is deposited on the surface including the intermediate conductor layer 8.
9 is selectively etched to provide an opening. Next, an aluminum layer is deposited on the surface including the opening, and is selectively etched to form an aluminum wiring 10 as an upper cotton wire electrically connected to the intermediate conductor layer 8 in the opening.

Here, as a mask for forming the intermediate conductor layer 8, a mask pattern used for forming the aluminum wiring 6 is reversed, and each portion is made thinner by several μm.

Note that here, a PSG (phosphorus silica glass) film or a silicon nitride film may be used instead of either the silicon oxide film 5 or 7.9, and the aluminum wiring 6 or 10 and the intermediate conductor layer 8 A polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, or the like may be used instead of the aluminum film.

〔Effect of the invention〕

As explained above, the present invention provides a first
By providing an intermediate conductor layer having a pattern opposite to the lower layer wiring (excluding the electrode lead-out portion) on the interlayer insulating film,
It has the effect of alleviating the level difference including the base of the lower layer wiring, preventing the occurrence of cracks and disconnections due to the level difference of the upper layer wiring provided on the second interlayer insulating film, and improving the reliability of the semiconductor/assembly integrated circuit. .

In addition, by grounding the upper layer wiring and the intermediate conductor layer,
It has the effect of shielding against alpha rays entering from the outside, and has the effect of increasing the heat dissipation effect.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a layout diagram and a cross-sectional view taken along the line A-A' of a semiconductor chip for explaining one embodiment of the present invention, and FIGS. 2(a) and (b) are a diagram of a conventional semiconductor chip. Layout diagram of a semiconductor chip and B- for explaining an example of an integrated circuit
It is a sectional view taken along the line B'. 1...P-type silicon substrate, 2...gate insulating film, 3
... Gate electrode, 4... N-type diffusion region, 5... Silicon oxide film, 6... Aluminum wiring, 7... Silicon oxide film, 8... Intermediate conductor layer, 9... Silicon oxide film, 0...aluminum film.

Claims (1)

[Claims] In a semiconductor integrated circuit having multilayer wiring, a lower wiring, a first interlayer insulating film provided on a surface including the lower wiring, and a first interlayer insulating film provided on a region other than the area of the lower wiring pattern. 1. A semiconductor integrated circuit comprising: a second interlayer insulating film provided on a surface including the intermediate conductor layer; and an upper layer wiring provided on the second interlayer insulating film.