JPH0287571A - semiconductor storage device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having a trench type storage capacitor, and furthermore, to a technique for improving the dielectric strength between storage capacitors or between memory cells in the semiconductor memory device. D.R.
AM (Dynamic Random Access Memory)
Concerning techniques that are effective when applied to

[Prior art]

Conventionally, in a DRAM having a trench-type storage capacitor, in order to electrically connect the storage capacitor and the selection transistor, a required portion above the insulating film formed on the side surface of the storage capacitor is removed, and one of the storage capacitors is removed. A structure is adopted in which an electrode is exposed, a diffusion region is formed in the substrate outside the storage capacitor so as to be in contact with the exposed electrode, and this diffusion region is connected to one source/drain region of the selection transistor. There is.

In addition, in order to insulate the storage capacitors of a RAM having a trench type storage capacitor, selective oxidation isolation (r, ,
a cos ) method has been commonly used.

In this method, impurities are doped only in the element isolation region using a nitride film as a mask, and then thermal oxidation is performed to create a thick isolation oxide film that functions as an insulating film. Extended Abstracts of t
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[Problem to be solved by the invention]

In the prior art, a diffusion region for electrically connecting a storage capacitor and a selection transistor is formed inside a semiconductor substrate, but the junction of the connection diffusion region is deeper than the source/drain region of the selection transistor. Put it away. Therefore, there is a problem in that the dielectric breakdown voltage between the connecting diffusion regions of adjacent memory cells is lowered due to the short channel effect, forming an undesirable parasitic transistor.

In addition, in a structure that uses conventional LOGO8 for isolation between elements of a DRAM with a trench-type storage capacitor, an oxide film region called a bird's beak is formed from the isolation region toward the element region during oxidation, causing the size of the isolation region to expand. The inventors of the present invention have discovered that there is a problem in that the minimum dimension that can be patterned cannot be reduced to a certain value or less because of this, and the degree of integration of memory cells cannot be increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can improve the dielectric strength between memory cells having trench-type storage capacitors and between storage capacitors.

Still another object is to provide a semiconductor memory device that can increase the degree of integration of memory cells having trench-type storage capacitors.

The above and other objects and novel features of the present invention will become apparent from the description of Water Lock US and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an electrode connecting the trench storage capacitor and the selection transistor is provided on the surface of the semiconductor substrate.

Further, an electrode layer for element isolation is provided between the storage capacitors with a thin insulating film interposed therebetween, and a predetermined potential that can prevent channel induction is applied to the element isolation electrode.

Furthermore, an insulating film to serve as a dielectric is formed on the inner surface of the storage capacitor formation groove, an impurity region that becomes the first electrode of the storage capacitor is formed on the outside of this insulating film, and all the storage A conductor is deposited as a second electrode common to the capacitors, and a predetermined potential is applied to the conductor to suppress channel induction.

[For production]

According to the above-mentioned means, since no channel induction region exists between mutually adjacent connection electrodes formed on a semiconductor substrate, it is possible to improve the dielectric breakdown voltage between adjacent memory cells.

In addition, the electrode layers and conductors located between mutually adjacent storage capacitors are forced to form a depletion layer in the semiconductor substrate located below them due to a predetermined potential applied thereto, thereby forming a storage capacitor. It acts to improve the dielectric strength between them.

This improvement in dielectric strength between memory cells and between storage capacitors serves to reduce the spacing between memory cells, thereby improving the degree of integration of memory cells having trench-type storage capacitors.

[Embodiment 1] FIG. 1 shows a longitudinal cross-sectional view of a main part of a DRAM which is an embodiment of the present invention.

Although not particularly limited, the DRAM shown in this figure is a one-transistor type memory cell, and is constituted by an N-channel selection MISFET Qi formed on a P-type semiconductor substrate 1 and a trench-type storage capacitor Ci. Above selection M
In the region between I S F E T Q i and the storage capacitor Ci, a surface oxide film 2 and an element isolation electrode layer (hereinafter also referred to as an isolation electrode layer) 3 made of polycrystalline silicon are laminated and formed. ing. According to this embodiment, a low level ov corresponding to the ground potential of the circuit is applied to the isolation electrode layer 3. As a result, a depletion layer is forcibly formed in the semiconductor substrate 1 below the electrode layer 3, thereby suppressing undesired induction of a channel in the semiconductor substrate 1 below the isolation electrode layer 3.

In other words, the isolation electrode layer 3 substantially prevents an on-state parasitic transistor from being formed in the region. Further, a channel stopper 41 in which P-type impurities are diffused at a high concentration is formed below the isolation electrode layer 3. This channel stopper 41 increases the threshold voltage of the channel region of the parasitic transistor, thereby making the channel induction suppressing effect by the isolation electrode layer 3 more reliable. Above selection MI
The SFET is composed of source/drain regions 26 and 27 and electrodes 1 to 28 formed between them with a gate oxide film 21 made of silicon oxide interposed therebetween. The upper surface of the gate electrode 28 is an interlayer insulating film 2 made of silicon oxide.
9, and the source/drain regions 26 and 27 are covered with LDD (Lightly Doped Drain) on the side surfaces of the gate electrode 28 and interlayer insulating film 29.
) A sidewall 31 made of silicon oxide is formed to serve as a mask for forming the structure.

The storage capacitor Ci is arranged at a predetermined distance from the selected MISFET Qi with the surface oxide film 2. The above isolation electrode layer 3. The insulating film 4 is formed so as to be embedded in a storage capacitor forming groove 6 opened in the semiconductor substrate 1 on which the insulating film 4 is deposited. A nitric oxide film 8 made of silicon oxide is formed on the entire side wall of the storage capacitor forming groove 6, and a polycrystalline silicon film 8 with a required thickness is formed on the lower part of the inner surface and on the bottom side of the forming groove 6. A concave second electrode layer 10 is formed. A dielectric material 1 made of nitride and silicon oxide is provided on the surface of the second electrode layer 10 and the nitric oxide film 8.
3 is formed, and polycrystalline silicon, which will become the first electrode layer 15, is buried in the portion surrounded by the dielectric 13 so as to be almost the same as the insulating film 4, and the surface of the first electrode layer 15 is is oxidized and becomes an insulating film 16. The first electrode layer 15
゜The above dielectric 13. The second electrode layer 10 constitutes the replacement volume ici, and the storage capacitance Ci of the substrate 1
An N-type semiconductor region connected to the second electrode layer 10 is formed near the bottom and serves as a plate electrode wiring 9 common to all storage capacitors.

The above accumulation field ffi Ci and the above selection M I S F E
Electrical connection with TQi is made on the surface of the semiconductor substrate 1, for example, the storage capacitor tC1, a connection electrode 23 made of polycrystalline silicon formed on the substrate 1, and an N-type semiconductor formed below it. This is done by area 24. The surface of the connection electrode 23 is oxidized to form an insulating film 25. The silicon oxide insulating film 16 above the storage capacitor Ci is shaved so that the constrained half near the selection MISFET exposes the first electrode layer 15, and conduction with the connection electrode 23 is established here. An N- type semiconductor region 24 formed under the connection electrode 23 is connected to the source/drain region 26 of the selection transistor.

A surface protective film 32 made of silicon oxide is provided on the elements formed on the substrate except on the drain/source region 27 of the selected M_SFET_Qi which is connected to a bit line (not shown). Fully formed.

In this way, by forming the connection electrode 23 on the upper side of the semiconductor substrate 1 and coupling the selection M FE T Q i with the storage capacitor C1, the connection electrode 23, which was conventionally formed inside the semiconductor substrate, can be used. There is no deep junction between the diffusion regions, and the reduction in dielectric strength between the diffusion regions due to the short channel effect is eliminated.

For example, P-type impurities are ion-implanted to a high degree into the substrate 1 in the selected M5FETQi formation region to form a channel stopper 42. This channel stopper 42 is a threshold value of a parasitic transistor formed by the plate electrode wiring 9 made of upper and lower N-type semiconductor regions of the storage capacitor Ci and the N-type semiconductor region 2.1°26.27 on the surface of the substrate 1. This works to prevent channels from being undesirably induced by increasing the voltage, and also improves resistance to soft errors caused by alpha rays.

In this figure, a sidewall 19 is shown on the side surface of the silicon oxide insulating film 16, but this sidewall is used to insulate the isolation electrode layer 3 from the gate electrode etc. that will be formed in a later process. It is formed on the side surfaces of the electrode layer 3 and the insulating film 4, and is also formed on the side surface of the insulating film 16 at the same time in the process.

Next, the manufacturing process of the DRAM shown in the above embodiment will be explained based on FIGS. 2(a) to 2(f).

As shown in FIG. 2(a), an oxide film 2 is formed on the surface of a semiconductor substrate 1, and then a polycrystalline silicon film 3 is deposited, and then phosphorus treatment is performed to transform the polycrystalline silicon film 3 into an N-type semiconductor. The resistance value is lowered by changing the resistance value to form the isolation electrode layer 3.

By constantly applying OV to the isolation electrode M3, a depletion layer is formed in the semiconductor substrate 1 below the Vi, m-pole layer 3, and a parasitic transistor in an on state is formed between elements on the substrate. deter things. Next, an insulating film 4 made of silicon oxide and a nitride film 5 are deposited on the entire surface, and then storage capacitor formation grooves 6 are formed at required positions by reactive ion etching (hereinafter referred to as RIE). Furthermore, by performing RIF after depositing a thin layer of silicon oxide on the inner surface of the capacitance forming groove 6 and the entire surface of the substrate, the silicon oxide film on the surface of the substrate and the bottom of the capacitance forming groove 6 is removed. A silicon oxide film that serves as a nitrate film 8 remains on the side surface of the storage capacitance formation groove 6 .

Next, as shown in FIG. 2(b), a polycrystalline silicon film is thinly deposited on the capacitance forming groove 6, the inner surface of the nitrate film 8, and the entire surface of the substrate, and then a phosphorus treatment is performed to form the capacitance forming groove 6. P is diffused into the substrate 1 from the bottom surface to form an N-type semiconductor region.

Since the N-type semiconductor region spreads out from the bottom surface of the capacitance formation trench 6 to the periphery, the N-type semiconductor region spreads out from the bottom of the other adjacent capacitance formation trench 6.
A plate electrode wiring 9 common to all storage capacitors is formed connected to the type semiconductor region. Subsequently, a photoresist film is deposited only inside the storage capacitor formation groove 6, and RIE is performed.
A required upper portion of the polycrystalline silicon film on the inner surface of the forming groove 6 is removed. Next, the photoresist film was removed, and the remaining polycrystalline silicon film was used as the second layer of the storage field tCi.
This is referred to as an electrode layer 10.

Next, as shown in FIG. 2(c), a nitride film is deposited thinly on the inner surface of the second electrode layer 10 and the nitride film 8, and on the entire surface of the substrate, and the surface of the nitride film is oxidized to form silicon oxide. However, the film made up of the two layers serves as the dielectric 13 of the storage capacitor Ci through a post-process. Subsequently, a thin layer of polycrystalline silicon is deposited on the surface of the nitride film whose surface is made of silicon oxide, and is changed into an N-type semiconductor by phosphorus treatment to prevent the generation of a depletion layer. Polycrystalline silicon is deposited throughout the interior, and the polycrystalline silicon functions as the first electrode layer 15 of the storage capacitor Ci. Next, by RIE, the dielectric 13 and the first capacitance on the surface of the substrate and in the capacitance forming groove 6 are removed. l!
The pole layer 15 is removed to approximately the same height as the surface of the isolation electrode layer 3. Next, as shown in FIG. 2(d), the surface of the first electrode layer 15 is oxidized to form an insulating film 16.
Oxide film 2 on region 20 where selection MIsFETQi is formed
．． Isolation electrode layer 3. Then, the silicon oxide insulating film 4 is removed to expose the semiconductor substrate 1, and the insulating film 16 and the nitrate oxide film 8 are removed in a required region adjacent to the selected MI S FET forming region 20 on the storage capacitor Ci. Then, the first electrode layer J5 is exposed. In this step, the side surfaces of the isolation electrode layer 3 are also exposed, and the selection M I S to be formed in a later step
Since it is necessary to insulate the gate electrode of FETQ 3, etc., silicon oxide is deposited on the entire surface of the semiconductor substrate 1, and then RIE is performed to form the oxide film 2. The above isolation electrode layer 3. Then, sidewalls 19 are formed on all sides of the insulating film 4 to be the remaining portion of the silicon oxide etched. Incidentally, the sidewall 19 (1) is simultaneously formed on the side surface of the insulating film 16 above the storage capacitor Ci.

Next, as shown in FIG. 2(e), after depositing a silicon oxide film 14 on the entire surface of the substrate 1, the selected MI S F E
An opening 4o is formed in a region where an electrode for connection between T Q i and the storage capacitor ci is to be formed, exposing the first electrode layer 15 and the semiconductor substrate 1 adjacent to the electrode layer.

Subsequently, the opening 4o is formed on the connection electrode formation region 40.
After forming the connection electrode 23 made of larger polycrystalline silicon, the surface of this connection electrode 23 is oxidized to form a surface oxide film 2.
5. Next, an N- type semiconductor region 24 for connection is formed on the semiconductor substrate below the connection electrode 23 by phosphorus treatment. Furthermore, high energy (200
keV) boron ions at a dose of lX1013/
A channel stopper 41 under the isolation electrode 3 and a channel 42 under the selected MJS FET formation region are formed by implanting to a depth of approximately d.

The channel stopper 41 serves to increase the threshold voltage of the channel region of a parasitic transistor undesirably formed between elements on the substrate, thereby further ensuring the channel induction suppressing effect by the isolation electrode 3.
The channel 1-flange 42 is the threshold voltage of a parasitic transistor formed by the plate electrode wiring 9 made of an N-type semiconductor region under the storage capacitor Ci and the N-type semiconductor regions 24, 26, 27 on the substrate surface. It works to prevent undesired channel induction by increasing α.
This improves resistance to soft errors caused by lines.

Subsequently, gate oxidation is performed to convert the silicon oxide film 14 in the selected MISFET formation region into a gate oxide film 21.

Next, as shown in FIG. 2(f), polycrystalline silicon and silicon oxide are laminated and deposited on the semiconductor substrate 1 and formed into a predetermined pattern to form a gate electrode 28 and an interlayer insulating film 29, respectively. Next, the gate electrode 28 and the interlayer insulating film 2
Using 9 as a mask, insert phosphorus into the semiconductor J-le board】L,
N- type semiconductor regions which will become the source/drain regions 26 and 27 of the selected MTSF E T Q i are formed. Subsequently, after depositing a silicon oxide film on the surface and side surfaces of the gate electrode 28 and interlayer insulating film 29, RIE is performed to remove the remaining silicon oxide etching only on the side surfaces of the gate electrode 28 and interlayer insulating film 29. A side wall 31 is formed. Furthermore, arsenic is implanted onto the semiconductor substrate 1 using the sidewall 31 as a mask to form an N<0> type semiconductor region in the source/drain region 26.27 of the selected MTS FET Qi, thereby forming an LDD structure. After the formation, a silicon oxide surface protection film 32 is deposited over the entire surface of the substrate element except on the source/drain regions 27.

According to the above embodiment, the following effects are obtained.

(1) The storage capacitor Ci and the selected MrSFETQi and c7) are electrically connected by the storage capacitor tci and the connection electrode 23 formed on the semiconductor substrate 1, and the connection N-type semiconductor region 24 formed below the storage capacitor tci. This eliminates the need for a diffusion region for connecting the storage capacitor and the selected MISFET, which was conventionally formed deep within the semiconductor substrate, and it is possible to increase the dielectric breakdown voltage between adjacent memory cells.

(2) Since a low level Ov corresponding to the ground potential of the circuit is always applied to the isolation electrode layer 3, a depletion layer is forcibly formed in the semiconductor substrate 1 below the electrode layer, and the isolation It works to prevent undesired channels from being induced in the semiconductor substrate 1 under the electrode layer 3. In other words, formation of an on-state parasitic transistor is suppressed. Therefore, conventionally m L OCO
Compared to the isolation region structure using S, the dimension between elements can be made smaller, and the degree of integration of a DRAM having a trench-type storage capacitor can be increased.

(3) The channel stopper 41 under the isolation electrode layer 3 raises the threshold voltage of the parasitic transistor and further ensures the channel induction suppressing effect by the isolation electrode layer 3.
The channel stopper 42 in the FET formation region undesirably increases the threshold voltage of the parasitic transistor formed by the plate electrode wiring 9 made of the N-type semiconductor region under the storage field tCi and the N-type semiconductor region on the substrate surface. This works to prevent a channel from being induced in the channel, thereby making it possible to further improve the withstand voltage between the selected MISFETs Qi.

[Embodiment 2] FIG. 3 shows a vertical sectional view of the main part of a DRAM which is another embodiment of the present invention.
The difference from the embodiment shown in the figure is the method of forming the isolation electrode layer.

Although not particularly limited, the DRAM shown in this figure is a one-transistor type memory cell as in Example 1, and is an N-channel type selection MISF formed on a P-type semiconductor substrate.
It is constituted by ETQi and I~wrench type storage capacitor Cj.

Note that the same reference numerals are used for the same members as in the above embodiment, and detailed description thereof will be omitted.

In this embodiment, the isolation electrode layer includes the trench type storage capacitor Ci and the selected MISFETQ.
It differs from the above embodiment in that it is formed on the element isolation region after the formation of i. In this embodiment, the isolation electrode layer 63 is provided on the element isolation region between the storage capacitors and between the storage capacitor Ci and the selection MISFET.
It is formed on a protective film 61 that covers the connection electrode 60 with Q i. As in the above embodiment, the isolation electrode layer 63 is always applied with Ov as a low level corresponding to the ground electrode potential of the circuit, so that a depletion layer is forcibly formed in the semiconductor substrate 1 below the electrode layer, and It works to prevent undesired channels from being induced in the semiconductor substrate 1 under the isolation electrode layer 3. In other words, the isolation electrode 63 substantially prevents an on-state parasitic transistor from being formed in the region. A channel stopper 65 made of a P+ type semiconductor region is formed below the isolation electrode layer 63 to increase the threshold voltage of the channel region of the parasitic transistor. The induction prevention effect is further ensured.

A channel stopper 66 made of a P" type semiconductor region is also formed in the substrate in the selected MI S FET formation region, and a channel stopper 66 made of a P" type semiconductor region is formed between the plate electrode wiring 9 made of an N type semiconductor region of the storage capacitor Ci and the N type semiconductor region on the substrate. It works to increase the threshold voltage of the parasitic transistor formed between the source/drain region 27.55 made of a semiconductor region and prevent undesired channel induction.

Next, r) the RAM shown in FIG. The Ii2 manufacturing process will be sequentially explained based on the entire process diagrams (a) to (d).

First, as shown in FIG. 4(a), the surface of the semiconductor substrate 1 is oxidized to form an oxide film 50, a nitride layer 51 is deposited, and first, a storage capacitor formation groove 6 is formed in the semiconductor substrate. 1. A nitric oxide film 8 made of silicon oxide is formed on the side surface of the capacitance forming trench 6 through the same steps as shown in FIG. 2(a).

Subsequently, a trench type storage capacitor is formed in the same process as shown in FIGS. 2(b) and 2(Q), and the surface of the first electrode 15 is oxidized to form an oxide film 52, as shown in FIG. Shown in (b).

Next, as shown in FIG. 4(c), the nitride layer 51 is removed, and the oxide film 5o on the surface of the semiconductor substrate 1 is subjected to gate oxidation to form a gate oxide film 53.

Subsequently, a process similar to that shown in FIG. 2(f) is performed to form a gate electrode 28 made of polycrystalline silicon and an interlayer insulating film 29 made of silicon oxide as an upper layer thereof. Select M OS F E '1'' by further typing phosphorus.
N- type semiconductor regions are formed to become source/drain regions 27 and 55, and the source/drain regions 55 are formed to extend to a position adjacent to the storage capacitor. Next, the gate electrode 28 is formed through a process similar to that shown in FIG. 2(f).
A sidewall 31 is formed on the side surface of the interlayer insulating film 29, and arsenic is implanted onto the semiconductor substrate l using the sidewall 31 as a mask to form an N+ type semiconductor region in the source/drain region 27.55 of the selected MISFET. (2) After forming the DD groove structure, a silicon oxide film 54 is deposited on the entire surface of the substrate element.

Next, as shown in FIG. 4(d), the selection MI S
The silicon oxide film 54 on the source/drain regions 27 of F F, T is removed, and a contact hole 34 is opened. After forming a pad electrode 35 on the interlayer insulating film 29 and the sidewall 31 so as to contact the source/drain region 27 through this contact hole 34, a silicon oxide film 56 is deposited on the entire surface of the substrate element 6. A connection electrode formation region 57 spanning the storage capacitor C1 and the selection MISFET is opened to expose the first electrode layer 15 of the storage capacitor C4 and the source/drain region 55 of the selection MISFET, and the connection electrode formation region 57 A connection electrode 60 larger than the above is formed of polycrystalline silicon. Next, after depositing a protective film 61 made of silicon oxide on the entire surface,
Etching is performed so that the semiconductor substrate 1 is exposed in all element isolation regions.

T above! After oxidizing the exposed surface of the semiconductor substrate 1 to form a gate oxide film 62, high-energy boron ions are implanted at a high concentration to form a channel stopper 65 in the element isolation region, and the selected MISFET formation region A channel stopper 66 is formed in the substrate. Furthermore, an isolation electrode layer 63 made of polycrystalline silicon is formed on the element isolation region. ¥! Since Ov as a low level is always applied to the pole layer 63, the fatf! A depletion layer is forcibly formed in the semiconductor substrate 1 below the layer, and serves to prevent an undesired channel from being induced in the semiconductor substrate 1 below the isolation electrode layer. In other words, formation of an on-state parasitic transistor is suppressed.

The channel stopper 65 increases the threshold voltage of a parasitic transistor undesirably formed on the semiconductor substrate 1, thereby further ensuring the channel induction suppressing effect by the isolation electrode layer 63. The channel stopper 66 is a parasitic transistor formed between the plate electrode wiring 9 made of an N-type semiconductor region in the storage field tC1 and the source/drain region 27.55 made of an N-type semiconductor region on the semiconductor substrate 1. This increases the threshold voltage of the channel to prevent undesired channel induction.

According to the above embodiment, similar to the first embodiment, it is possible to increase the dielectric strength between adjacent memory cells of a DRAM having a trench type storage capacitor, and also to improve the degree of insulation. It's something you get.

[Embodiment 3J FIG. 5 shows a vertical sectional view of the main part of a DRAM which is another embodiment of the present invention, and this embodiment and FIGS.
The shape and structure of the storage capacitor and isolation electrode layer differ from the embodiment shown in the figure.

Although the DRAM of this example is not particularly limited, Example 1
, 2, it is a one-transistor type memory cell and is formed on a P-type semiconductor substrate.
It is composed of an FET Q i and a trench storage capacitor Ci.

Note that the same reference numerals are used for the same members as in the above embodiment, and detailed description thereof will be omitted.

A dielectric 73 is formed on the side and bottom surfaces of the storage capacitor formation groove 6 provided in the semiconductor substrate 1, and a second electrode 74 made of polycrystalline silicon is embedded inside the dielectric 73. The second electrode 74 is coupled to a plate electrode 75 common to all storage capacitors, and this plate electrode 75 also extends to the region between mutually adjacent storage capacitors Ci.

An N+ type semiconductor region is formed outside the dielectric 73 of the storage capacitor Ci and serves as the first electrode 72 of the storage capacitor.
It is in contact with the drain region 55. The plate electrode 7
The portion extending above the inter-element region of No. 5 is forcibly placed on the semiconductor substrate underlying the electrode layer 75 by constantly applying a low level of 0■ corresponding to the ground potential of the circuit. It also functions as an isolation electrode that forms a depletion layer and prevents undesired channel formation in the substrate 1.

A channel stopper 65 in which P-type impurities are diffused at a high concentration is formed in the lower layer of the isolation electrode 75 via the nitride layer 71, and this channel stopper 65 increases the threshold voltage of the parasitic transistor. The effect of suppressing channel induction by the isolation electrode 75 is further ensured.

There is also P in the substrate in the selected MISFET Qi formation region.
Channel stopper 66 with mold impurities diffused in high concentration
is formed, and the first electrode 72 made of the N-type semiconductor region of the semicircular capacitance C1 and the selected M I S F F: T
It works to increase the threshold voltage of the parasitic transistor formed with the source train region 27.55 made of the N-type semiconductor region of Qi, thereby preventing undesired channel induction.

Next, the manufacturing process of the DRAM shown in FIG. 5 is shown in FIG.
This will be explained in order based on a) to (d).

First, a silicon oxide film 70 and a nitride layer 71 are deposited on a semiconductor substrate j as shown in FIG. Highly concentrated boron ions are obliquely implanted to form an N1 type semiconductor region 72 that serves as the first electrode of the storage capacitor.

Subsequently, as shown in FIG. 6(b), a dielectric material 73 for the storage capacitance is formed on the semiconductor substrate 1 on which the silicon oxide film 7o and the nitride layer 71 have been deposited, and on the inner surface of the storage capacitor formation groove 6. After the nitride film 80 is deposited on the entire surface, surface oxidation is performed.

A polycrystalline silicon layer 74, which will become a plate electrode/isolation electrode WJ75, is deposited on the entire surface of the dielectric 73, and the portion deposited in the storage capacitor forming groove 6 becomes the second electrode 74 of the storage capacitor.

The isolation electrode layer 75 is always applied with Ov as a low level corresponding to the ground potential of the circuit, so that a depletion layer is forcibly formed on the lower semiconductor substrate, and the semiconductor substrate under the isolation electrode layer 75 is 1 to prevent undesired channel induction.

Further, as shown in FIG. 6(c), by etching, the semiconductor J of t in a required area adjacent to the storage capacitor Ci,
(Plate 1 is exposed and selected M I S FET formation region 81
However, since the nitride layer 71 has a different etching rate from the isolation layer 75 made of polycrystalline silicon, it acts as a barrier to prevent the semiconductor substrate 1 from being etched more than necessary. . At this time, the side surface of the plate electrode/isolation electrode layer 75 is also exposed.

Next, as shown in FIG. 6(d), the above selected MTSFE
After the surface of the semiconductor substrate 1 in the T formation region 81 is oxidized to form the gate insulating film 76, the selected MISF gate electrode 282 is insulated through the same process as shown in FIG. 2(f). Membrane 29, sidewall 31.
Source/drain regions 27.55 are formed, and the source/drain regions 55 are formed so as to be in contact with the first electrode 72 of the storage capacitor Cj. Further, high-energy boron ions are implanted at a high concentration to form a channel stopper 65 below the isolation electrode layer 75 and a channel stopper 66 in the selected MISFETQi formation region. Channel stopper 65 below the isolation electrode yfa75
The threshold voltage of the parasitic transistor undesirably formed on the semiconductor substrate 1 is increased to further ensure the channel induction suppressing effect by the isolation electrode layer 75, and the channel transistor in the selection MISFET Qj formation region is increased. 1 to the collar 66 are connected to the first electrode 72 made of the N-type semiconductor region of the storage capacitor fCi and the selected M I S F'' E
The threshold voltage of the parasitic transistor formed between T Q i and the source/drain region made of the N-type semiconductor region is increased to prevent undesired channel induction. Finally, a protective film 77 and pad electrode 35 are formed in the same process as shown in FIG. 4(d).

According to the above embodiment, as in the first and second embodiments, the reliability of r) RAM having a trench type storage capacitor is improved and the degree of integration can be improved.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist of the invention. , I).

For example, in this embodiment, the selected MTS FET is an N-channel type, but a P-channel type may also be adopted. Further, in Example 2, the material of the isolation electrode layer is polycrystalline silicon, but it is not necessarily limited to this, and a conductive material such as aluminum can be appropriately employed.

In the above description, the invention made by the present inventor was mainly applied to DRAM, which is the background field of application, but the present invention is not limited thereto, and is applicable to semiconductor memories such as pseudo SRAM. Can be widely used in equipment.

The present invention can be applied to at least a condition having a trench type memory cell.

〔Effect of the invention〕

A brief explanation of the effects obtained by two representative inventions among the inventions disclosed in this application is as follows.

That is, since the electrode connecting the trench storage capacitor and the selection transistor is provided on the surface of the semiconductor substrate, the diffusion region for connecting the trench storage capacitor and selection MISFET, which was conventionally formed deep within the semiconductor substrate, is eliminated. This has the effect of increasing the dielectric breakdown voltage between adjacent memory cells.

In addition, electrode layers or conductors are provided between adjacent storage capacitors or memory cells, and these electrode layers or conductors are provided with a predetermined potential to suppress undesired channel induction in the underlying semiconductor substrate. Therefore, there is an effect that the insulation breakdown voltage between the storage capacitors and between the selection transistors is improved.

Since a region containing a high degree of impurity that determines the conductivity type of the semiconductor substrate is formed in the semiconductor substrate under the electrode layer and the conductor layer, the effect of suppressing undesired channel induction is further ensured. There is.

By improving the dielectric strength between the storage capacitors and between the selection transistors, it is possible to reduce the inter-element dimensions compared to the conventional LOGO8 element isolation structure, thereby increasing the integration density of DRAMs with trench-type storage capacitors. It has the effect of being able to give.

[Brief explanation of drawings]

FIG. 1 is a longitudinal cross-sectional view showing the main parts of a DRAM that is an embodiment of the present invention. FIGS. 2(a) to (f) show the DRAlv! shown in FIG.
'1M construction process vertical cross-sectional views showing an example of the process. FIG. 3 is a vertical cross-sectional view showing essential parts of a DRAM according to another embodiment of the present invention, and FIGS. 4(a) to (d) are vertical cross-sectional views sequentially showing an example of the DRAM manufacturing process shown in FIG. 3. 5 is a vertical sectional view showing the main parts of a DRAM which is another embodiment of the present invention, and FIGS. 6(a) to 6(d) sequentially show an example of the DRAM manufacturing process shown in FIG. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Surface oxide film, 3... Isolation electrode layer, 4... Silicon oxide insulating film,
5... Nitride film, 6... Storage capacitor forming groove, 8
...Nitric oxide film, 9...Plate electrode wiring, 10...
2nd electrode layer, 13, dielectric, 15... 1st electrode layer, 16
...Silicon oxide insulating film, 19...Side wall, 20...Selected MT 5FET formation region, 21...
Gate oxide film, 23... Connection electrode, 24... N-type semiconductor region for connection, 26.27... Source/drain region, 28... Gate electrode, 29... Interlayer insulating film,
31... Side wall, 34... Contact hole, 35... Pad electrode, 40... Connection electrode dose hole, 41.42... Channel stopper, 50...
Surface oxide film, 51... Nitride layer, 52... Surface oxide film, 53... Gate oxide film, 55... Source/drain region, 57... Connection electrode formation region, 60...
... Connection electrode, 61 ... Protective film, 62 ... Gate oxide film 1.63 ... Isolation electrode layer, 65.6
6... Channel stopper, 70... Silicon oxide film, 71... Nitride layer, 72... First electrode layer, 73... Dielectric, 74... Second electrode. 75... Plate electrode/isolation electrode layer, 7
6... Gate oxide film, 81... Selected MISFET formation region. Figure 2/C

Claims (1)

[Claims] 2. Claim 1: A trench-type storage capacitor and a selection transistor formed by forming an insulating film on the inner peripheral surface of a storage capacitor forming groove formed in a semiconductor substrate up to at least the surface of the semiconductor substrate. A semiconductor memory device in which a plurality of memory cells are arranged adjacent to each other, wherein a connection electrode for electrically connecting the selection transistor and the storage capacitor is formed on the semiconductor substrate. . 2. An insulating film is formed on the inner circumferential surface of a storage capacitor formation groove formed in a semiconductor substrate, and a plurality of trench-type storage capacitors and selection transistors are formed, with a pair of storage capacitor electrodes formed inside the insulating film via a dielectric. In a semiconductor memory device in which memory cells are arranged adjacent to each other, an electrode layer is formed on a semiconductor substrate between adjacent storage capacitors with a thin insulating film interposed therebetween. A semiconductor memory device in which a potential is applied to prevent channel induction in a semiconductor substrate under an electrode layer. 3. The semiconductor memory device according to claim 2, wherein a region containing a high concentration of an impurity that determines the conductivity type of the semiconductor substrate is formed in the semiconductor substrate under the electrode layer. 4. The semiconductor memory device according to claim 3, wherein the thin insulating film and the electrode layer also extend on the semiconductor substrate between the mutually adjacent selection transistors. 5. An insulating film is formed on the inner surface of the storage capacitor formation groove formed in the semiconductor substrate, an impurity region that becomes the first electrode of the storage capacitor is formed on the outside of the insulating film, and an impurity region is formed on the inside of the insulating film. A conductor serving as a second electrode of the capacitor is commonly connected to all storage capacitors, and a thin insulating film is formed under the conductor located between adjacent storage capacitors. A semiconductor memory device in which a conductor is provided with a potential that prevents channel induction in a semiconductor substrate below the conductor. 6. The semiconductor memory device according to claim 5, wherein a region containing a high concentration of an impurity that determines the conductivity type of the semiconductor substrate is formed in the semiconductor substrate under the conductor.