JPH0287630A - Manufacture of mis field-effect transistor - Google Patents

Abstract

PURPOSE:To manufacture this transistor whose gate breakdown strength is high with a good yield and easily by a method wherein a second gate electrode layer, a source electrode layer and a drain electrode layer are formed on a first gate electrode layer, an ion-implanted region for source use and an ion- implanted region for drain use. CONSTITUTION:By an ion implantation treatment of an n-type impurity by making use of a mask layer 22 and insulating layers 7, 8 as a mask, a source region 10 and a drain region, of an n-type, are formed, inside a semiconductor substrate 1 from its surface side, in both positions sandwiching a gate electrode layer 5. Then, the mask layer 22 is removed from the upper part of the gate electrode layer 5; after that, a gate electrode layer 12, a source electrode layer 13 and a drain electrode layer 14 are formed on the gate electrode layer 5, the source region 10 and the drain region 11. Insulating layers 23 and 24 may be formed on opposite side faces of the gate electrode layer 5 by a heat treatment before a comparatively thick insulating layer is formed on an insulating layer 2 so as to cover the mask layer 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing an MIS field effect transistor. (Prior art 1) Conventionally, a method for manufacturing an MIS field effect transistor has been proposed, which will be described below with reference to FIG. (FIG. 3A). Then, on the semiconductor substrate 1, a relatively thin insulating layer 2 made of, for example, S02 and a conductive layer 3 made of, for example, polycrystalline S1 or amorphous 3i are formed in that order ( 3B). Next, a mask layer 4 made of, for example, photoresist is formed on the conductive layer 3 so as to divide the conductive layer 3 into two when viewed from above (FIG. 3C). Next, by etching the conductive layer 3 using the mask layer 4 as a mask, the conductive layers 3 to 1, the mask FI
Forming the gate electrode layer 5 under J4 (Figure 3D)
. Next, mask layer 4 is removed from above gate electrode layer 5 (FIG. 3E). Next, a relatively thick insulating layer 6 of, for example, 5 in 2 is deposited on the insulating layer 2, covering the gate electrode layer 5.
form (Fig. 3F). Next, by performing a reactive ion etching process on the insulating layers 6 and 2, insulating layers 7 and 8 are formed extending from the insulating layer 6 onto opposite side surfaces of the gate electrode layer 5, respectively, and the insulating layers 2 to form a gate insulating layer 9 below the gate electrode layer 5 and insulating layers 6 and 7 (
Figure 3G). Next, an n-type impurity ion implantation process is performed on the semiconductor substrate 1 using the gate electrode layer 5 and the insulating layers 7 and 8 as masks, so that a gate electrode is implanted into the semiconductor substrate 1 (into the A substrate 1 from the upper surface side of each). At both positions sandwiching the layer 5, a source region 10 and a drain region 11, both of which are n-type, are formed (third
Figure H) In this case, source region 10 and drain region 11
can be obtained as activated by performing a heat treatment on the semiconductor substrate 1 during the ion implantation process or after (), or can be obtained as a substantially activated one without performing such a heat treatment. Next, a gate electrode layer 12, a source electrode layer 13, and a drain electrode layer 14 are formed on the gate electrode layer 5, the source region 10, and the drain region 11, respectively (FIG. 3I). In this case, the gate electrode 1i112, the source electrode layer 13, and the drain electrode layer 14 are formed by selectively depositing a metal such as tungsten or molybdenum on the gate electrode layer 5, the source region 10, and the drain region 11, respectively. The metal can be obtained as a gold II layer made of the above-mentioned metal, or by depositing the above-mentioned metal successively on the gate electrode layer 5, the source region 10, and the drain region 11, and then performing a heat treatment. 11 are laminated with a gate electrode layer 5, a source region 10, and a drain region 1.
The region above 1 is silicided, and then the region of the metal deposited layer on the insulating layers 7 and 8 is removed by etching to form the metal silicide layer 1q. Further, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are connected to the source region 10 and the drain region 11.
When forming the above-mentioned metal layer from an activated state, there is no need to perform special heat treatment on the semiconductor substrate 1 both during and after the formation of the metal layer, and the gate electrode layer 12. When forming the source electrode layer 13 and the drain electrode layer 14 as the metal silicide layer described above from the state where the source region 10 and the drain region 11 are activated, the semiconductor substrate is Since the heat treatment is applied to the semiconductor substrate 1, there is no need to perform any special heat treatment on the semiconductor substrate 1 both during and after the formation of the metal silicide layer. 14 is formed as the above-mentioned metal layer from a state where the source region 10 and drain region 11 are not activated. After forming the layers, heat treatment is performed on the semiconductor substrate 1 to form the source region 10 and the drain region 1.
1 as activated. The above is the conventionally proposed method for manufacturing MIS field effect transistors. It is clear that the MIS type field effect transistor (■ in Figure 3) manufactured by the conventional MIS type field effect transistor manufacturing method shown in Figure 3 exhibits the performance as an MIS type field effect transistor. , source region 10
The drain region 11 does not mask only the gate electrode layer 5 with respect to the semiconductor substrate 1, but rather covers the gate electrode layer 5 including the insulating layers 7 and 8 formed on opposite sides of the gate electrode layer 5. Since the source region 10 and the drain region 11 are formed by ion implantation of n-type impurities using the insulating layers 7 and 8 as masks, the opposite side ends of the source region 10 and the drain region 11 face each other with respect to the gate electrode layer 5. It is formed without unnecessary extension inward from the bottom of the side surface.For this reason, it functions as a MIS type field effect transistor with good characteristics.In addition, the MISP!:! electric field described above in Fig. 3 According to the manufacturing method of the effect transistor, as described above, the opposing side ends of the source region 10 and the drain region 11 are unnecessarily extended inward from below the opposing sides of the gate electrode layer 5. MI
S type field effect transistor 1. It can be manufactured with good properties. [Problems to be Solved by the Invention] However, in the case of the conventional manufacturing method of the MIS type field effect transistor shown in FIG. After the step of forming over the layer 5 (FIG. 3F), a reactive ion etching process is applied to the insulating layer 6 so that the insulating layer 6 extends from the insulating layer 6 onto opposite sides of the gate electrode layer 5, respectively. While forming the insulating B layers 7 and 8, from the insulating layer 2,
In the step of forming the goo 1 to the insulating layer 9 under the gate electrode layer 5 (FIG. 3G), if the gate electrode layer 5 has pinholes, the ions used in the reactive ion etching process or The radicals pass through the pinhole of the gate electrode layer 5 and irradiate the area under the gate electrode layer 5 of the insulating layer 2, so that the gate insulating layer 9 is formed as a bottle ball or having weak points. , therefore,
There was a fear that the gate insulator FJ9 would be formed with only a low withstand voltage. Therefore, there was a risk that the MIS field effect transistor would be manufactured with a low gate breakdown voltage. Further, by ion implantation of n-type impurities into the semiconductor substrate 1 using the gate electrode layer 5 and the insulating layers 7 and 8 as masks, the source region 10 and the drain region 11 are implanted into the semiconductor substrate 1 from the upper surface side. After the forming step (FIG. 3H), a gate electrode layer 12, a source electrode layer 13 are formed on the gate electrode layer 5, the source region 10, and the drain region 11.
and the step of forming the drain electrode layer 14 (third step)
In Figure ■), on the insulating layer 7, a layer made of the material of the gate electrode layer 12 and the source electrode layer
A layer made of the material of the gate electrode layer 12 and the drain electrode layer 14 is formed on the insulating layer 8 by extending them to a short distance of 18-1' between the gate electrode layer 12 and the source electrode [13]. There was a fear that the layer 12 and the drain electrode layer 14 would be formed in an extended manner so as to short-circuit them. Therefore, there was a fear that the MIS field effect transistor would be manufactured without the function of a MrS field effect transistor. Therefore, the present invention aims to propose a novel MIS type field effect transistor that does not have the above-mentioned drawbacks. [Means for Solving the Problems 1] A method for manufacturing an M r s rr': field effect transistor according to the first invention of the present application includes the steps described below. That is, (1) forming a relatively thin first insulating layer, a conductive layer, and a nitride layer in that order on a semiconductor substrate having a first conductivity type, and (2) forming the nitride layer in that order. on the layer,
A step of forming a first mask layer; and (2) a first etching process for the nitride layer using the first mask layer as a mask, from the nitride to a second etching layer under the first mask layer. A step of forming a mask layer; and (2) a second etching process for the conductive layer using the first and second mask layers as masks, from the conductive layer to the first layer under the second mask layer. (2) forming a relatively thick second insulating layer on the semiconductor substrate after removing the first mask layer from above the second mask layer; The second insulating layer is formed by forming the second insulating layer covering the first insulating layer, the first gate electrode layer, and the second mask layer, and (2) performing a reactive ion etching process on the first and second insulating layers. From the layer
forming third and fourth insulating layers extending on opposite side surfaces of the first gate electrode layer and the second mask layer, respectively; forming a gate insulating layer under the gate electrode layer and the third and fourth insulating layers; (1) using the second mask layer and the third and fourth insulating layers as masks for the semiconductor substrate; By ion implantation of an impurity that imparts a second conductivity type opposite to the first conductivity type, a second conductive layer is implanted into the semiconductor substrate from the upper surface side at both positions sandwiching the first gate electrode layer. (1) forming a source region and a drain region having a conductivity type of 1; and (2) removing the second mask layer from above the first gate electrode layer;
Steps of forming an electrode layer, a source electrode layer, and a drain If IU l on the second gate 1 on the first gate 1 to electrode layer, the source ion implantation region, and the drain ion implantation region, respectively. has. Further, MIS type field effect 1 to according to the second invention of the present application
The method for manufacturing a transistor includes the steps described below. That is, in the method for manufacturing an MIS field effect transistor according to the first invention of the present application, after the step of forming the source region and drain region in the semiconductor substrate described above, After removing the first mask layer, the second mask layer is removed from the first gate electrode layer.
forming second and third insulating layers on opposing side surfaces of the first gate electrode layer by heat treatment using the mask layer as a mask; (1) forming an insulating layer covering the first, second, and third insulating layers, the first gate electrode layer, and the second mask layer; Extending the outer sides of the second and third insulating layers and the second mask layer from the fourth insulating layer onto opposing sides, respectively, by applying a reactive ion etching treatment to the layer for a time of 1η. forming fifth and sixth insulating layers,
forming a gate insulating layer under the first insulating layer, the first goo 1 to electrode layer and the second, third, fifth and sixth insulating layers; By ion implantation of an impurity that gives a second conductivity type opposite to the first conductivity type using the second, third, fifth, and sixth insulating layers as masks, the above-mentioned forming a source region and a drain region having a first conductivity type in the semiconductor substrate at both positions sandwiching the first goo 1-electrode layer from the upper surface side;
After removing the second mask layer from above the gate electrode layer, a second gate electrode VMIU is applied onto the first gate electrode layer, the source ion implantation region, and the drain ion implantation region. , and the steps of forming a source electrode layer and a drain electrode layer, respectively. [Action/Effect 1] MI according to the first invention of the present application and the second invention of the present application
M manufactured by the S-type field effect transistor manufacturing method
The IS type field effect transistor is manufactured using the M
It is clear that it exhibits the functionality of an IS type field effect transistor, and since the source region and drain region are formed according to the manufacturing method of the conventional MIS type field effect transistor described above in FIG. Since the source region and the drain region are formed without extending their opposite side ends unnecessarily inward from below the relatively self-weighting side surface of the gate electrode layer, it functions as an MIS field effect transistor. exhibits good characteristics. Further, according to the method for manufacturing MrS type field effect transistor according to the first invention of the present application and the second invention of the present application, the third invention
As in the case of the manufacturing method of the conventional MIS type field effect transistor described above in the figure, the source region and the drain region are formed so that their opposing side edges are lower than the opposing sides of the gate electrode layer, as described above. Since it can be formed without unnecessary extension inward, MrS type field effect transistors can be manufactured with good characteristics. However, in the method for manufacturing MIS field effect transistors according to the first invention and the second invention of the present application, a relatively thick insulating layer (the second invention of the present application) is formed on the second I8 edge layer formed on the semiconductor substrate. In the case of the manufacturing method of the MXS type field effect 1 helangistor according to the first invention, the second insulating layer, and in the case of the manufacturing method of the MIS type field effect 1 helangistor according to the second invention of the present application, the fourth insulating layer), After forming over the second mask layer, a reactive ion etching process is performed on the insulating layer to form an insulating layer extending from the insulating layer onto opposing sides of the second mask layer. In the case of the manufacturing method of the MIS type field effect transistor according to the first invention, the third and fourth insulating layers, and in the case of the manufacturing method of the MrS type field effect transistor 1 to transistor according to the second invention of the present application, the fifth and sixth In the step of forming a gate insulating layer from the first insulating layer, the reactive ion etching process is performed using the second mask layer as a mask, so pinholes are not formed in the gate electrode layer. Since the first insulating layer is not irradiated by the ions or their radicals used in the reactive ion etching process, even if the gate insulating layer is In comparison, it is formed with a high withstand voltage. Therefore, the MIS field effect transistor can be manufactured as a transistor with a high gate breakdown voltage. Further, according to the method for manufacturing an MIS type field effect transistor according to the first invention of the present application and the second invention of the present application,
After forming a source region and a drain region in a semiconductor substrate, a step of forming a gate electrode layer, a source electrode layer, and a drain electrode layer on the source region and the drain region, respectively. gate electrode layer,
The source electrode layer and the drain electrode layer are arranged between the gate electrode layer and the source electrode layer, and between the gate electrode layer and the drain electrode layer 1 (
In the case of the conventional manufacturing method of the lvl l S-type field effect transistor described above in FIG. 8 steps less, therefore, MI
Easily manufacture S-type field effect transistors with high yield (
I can do J. (Example 1) Next, with reference to FIG. 1, the MIS according to the first invention of the present application
An example of a method for manufacturing a type field effect transistor will be described below. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. Manufacturing method of MIS type field effect transistor according to the first invention of the present application shown in FIG. 1 (31, having the following sequential steps. As with the manufacturing method of transistors, for example, single crystal S
1 and having, for example, an n-type semiconductor substrate 1 is prepared in advance (FIG. 1A). Then, on the semiconductor substrate 1, a relatively thin insulating layer 2 made of, for example, S02, a conductive layer 3 made of, for example, polycrystalline S1 or amorphous 3i, and a nitride layer 21 made of, for example, silicon nitride, are formed in that order. Next, a mask layer 4 made of, for example, photoresist is formed on the nitride layer 21 so as to divide the conductive layer 3 into two when viewed from above (the first Figure C) Next, by etching the nitride layer 21 using the mask layer 4 as a mask,
From the nitride layer 21 a further mask layer 22 under the mask layer 4 is formed (FIG. 1D). Next, by etching the conductive layer 3 using the mask layers 4 and 22 as masks, the conductive layer 3 to 1 and the gate electrode layer 5 under the mask layer 22 are formed (first
Figure E). Next, the mask layer 4 is removed from above the gate electrode layer 5 (FIG. 3E). Next, a relatively thick insulating layer 6 made of, for example, 3 i Q2 is placed on the insulating layer 2 between the mask layer 22 and the gate electrode layer 5. It is formed to cover the electrode layer 5 by the IK stacking method (FIG. 1G). Next, insulating layers 7 and 8 are formed extending from insulating layer 6 onto opposing side surfaces of mask layer 22 and gate electrode layer 5, respectively, by a reactive ion etching process on insulating layers 6 and 2. At the same time, a gate insulating layer 9 is formed from the insulating layer 2 to the electrode layer 5 and the insulating layers 6 and 7F (FIG. 1-1). Next, an n-type impurity ion implantation process is performed on the semiconductor substrate 1 using the mask layer 22 and the insulating layers 7 and 8 as masks. A source region 10 and a drain region 11, both of which are n-type, are formed at both positions sandwiching the
Figure ■) In this case, the source region 10 and the drain region 11
can be obtained as activated during the ion implantation process or by applying a heat treatment to one of the semiconductor substrates 1, or can be obtained as an activated one without performing such a heat treatment. Get as if it wasn't. Next, after removing the mask layer 22 from above the gate electrode layer 5, the gate electrode layer 5, the source region 10, and the drain region 1 are removed.
1, a gate electrode layer 12, a source electrode layer 13, and a drain electrode layer 14 are respectively formed (FIG. 1J). In this case, the Goo 1 to Electron 4IIIi layers 12, the source electrode layer 1
3 and drain electrode layer 14 are formed by selectively depositing 1 layer of metal, such as tungsten or pyriddenum, on gate electrode layer 5, source region 10, and drain region 11, respectively. or gate electrode layer 5, source region 10
and the drain region 1411, the metal X
The regions on the t-stacked goo 1-electrode layer 5, source region 10, and drain region 11 are silicided, and then the metal 1
By removing the regions on the laminated insulating layers 7 and 8 by etching, the above metal silicide is obtained as a metal silicide layer. The drain electrode layer 14 is connected to the source region 10 and the drain region 11.
When forming the above-mentioned metal layer from a state in which the gate ? I2 pole layer 12, source electrode layer 1
When forming the metal silicide layers 3 and 1/4 of the drain electrode layer 1/4 in the state where the source region 10 and the drain region 11 are activated, heat treatment is performed on the semiconductor substrate 1 when forming the metal silicide layers. Since the metal silicide layer is formed, there is no need to perform any special heat treatment on the semiconductor substrate 1 either during or after the formation of the metal silicide layer. When forming the layer 14 as the above-mentioned metal layer from a state where the source region 10 and drain region 11 are not activated, at the time of forming the metal layer,
The source region 10 and drain region 11 can be obtained as activated by subjecting the semiconductor substrate 1 to heat treatment or by subjecting the semiconductor substrate 1 to heat treatment after forming the metal layer. The above is an embodiment of the method for manufacturing an MIS type field effect transistor according to the first invention of the present application. According to the embodiment of the method for manufacturing an MIS field effect transistor according to the first invention of the present application, [Operations and Effects]
Since it is clear from what has been said in the section above, detailed explanation will be omitted, but the excellent functions and effects described in Section 1 are as follows. Also, the MIS type according to the first invention of the present application In the method of manufacturing a field effect transistor, since the gate electrode layer 12 is formed on the gate electrode 4ii layer 5 and limited by the insulating layers 7 and 8, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are , short circuit A3 can be easily formed without it. [Example 2j] Next, with reference to FIG.
An example of a method for manufacturing a type field effect transistor will be described below. In FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals and detailed explanations are omitted. The manufacturing method of the MIS type field effect transistor according to the second invention of the present application shown in FIG. Layer 5'' - mask layer 22
(FIG. 1F) and before taking the step of forming a relatively thick insulating layer 6 on the insulating layer 2 to cover the mask layer 22 (FIG. 1G), By heat treatment of the gate electrode layer 5 using the mask layer 22 as a mask, an insulating layer 23 is formed on the opposing sides of the gate electrode NA layer 5.
and 24 (FIG. 2B), the MI according to the first invention of the present application described above in FIG.
It has a process similar to the manufacturing method of S-type field effect 1-transistor. The steps of A Ttj3, FIG. 2 A, and FIG. 2 CSD, E, F, and G correspond to FIG. 1 F, G, H, I, and J, respectively. The above is an embodiment of the method for manufacturing an MIS field effect transistor according to the second invention of the present application. The method for manufacturing the MTS field effect transistor according to the second invention of the present application also provides the same operation and effect as the method for manufacturing the MIS field effect transistor according to the first invention of the present application described above in FIG. should be obvious. j3. In the method of manufacturing the MIS field effect transistor according to the second invention of the present application, when forming the insulating layers 23 and 2/'I, the thickness can be made as thick as desired, so that 1 to the electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 can be formed more easily without shorting J3. Note that the above description merely shows a few embodiments of the MrS type field effect transistor according to the present invention, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a line cross-sectional view showing sequential steps in an embodiment of the method for manufacturing MIS type field effect 1 to transistor according to the first invention of the present application. FIG. 2 is a cross-sectional view showing sequential steps in an embodiment of a method for manufacturing an MIS field effect transistor according to the second invention of the present application. FIG. 3 is a cross-sectional view showing sequential steps in a conventional MIS field effect transistor manufacturing method. 1... Semiconductor substrate 2... Insulating layer 3... Conductive layer 4... Mask layer 5 ......Gate electrode layer 6...Insulating layer 7...Insulating layer 8...Insulating layer 9 ......Gate insulating layer 10...Source region 11...Drain region 12...Gate electrode layer 73... ......Source electrode layer 14...Drain electrode layer 21...
...Nitride layer 22...Mask layers 23, 24...Insulating layer

Claims (1)

[Claims] 1. A step of sequentially forming a relatively thin first insulating layer, a conductive layer, and a nitride layer in that order on a semiconductor substrate having a first conductivity type; A step of forming a first mask layer on the nitride layer, and a first etching treatment of the nitride layer using the first mask layer as a mask, from the nitride to the first mask layer. By forming a second mask layer under the mask layer and performing a second etching process on the conductive layer using the first and second mask layers as masks, the conductive layer is removed from the second mask layer. forming a first gate electrode layer under a second mask layer; and after removing the first mask layer from above the second mask layer, forming a relatively thick second gate electrode layer on the semiconductor substrate; forming an insulating layer covering the first insulating layer, the first gate electrode layer, and the second mask layer; and performing a reactive ion etching process on the first and second insulating layers. Therefore, forming third and fourth insulating layers extending from the second insulating layer onto opposing side surfaces of the first gate electrode layer and the second mask layer, respectively; forming a gate insulating layer under the first gate electrode layer and the third and fourth insulating layers from the first insulating layer; forming the second mask layer on the semiconductor substrate; And by ion implantation of an impurity that gives a second conductivity type opposite to the first conductivity type using the fourth insulating layer as a mask, from the upper surface side of the semiconductor substrate,
At both positions sandwiching the first gate electrode layer, the first
forming a source region and a drain region having a conductivity type of; after removing the second mask layer from above the first gate electrode layer; A method for manufacturing an MIS field effect transistor, comprising the steps of forming a second gate electrode layer, a source electrode layer, and a drain electrode layer on the implantation region and the drain ion implantation region, respectively. 2. A step of sequentially forming a relatively thin first insulating layer, a conductive layer, and a nitride layer in that order on a semiconductor substrate having a first conductivity type, and on the nitride layer, A step of forming a first mask layer, and a first etching process for the nitride layer using the first mask layer as a mask, remove the nitride from the second mask layer under the first mask layer. and a second etching process for the conductive layer using the first and second mask layers as masks, from the conductive layer to the area under the second mask layer. forming a first gate electrode layer; and after removing the first mask layer from above the second mask layer, using the second mask layer as a mask for the first gate electrode layer; forming second and third insulating layers on opposing side surfaces of the first gate electrode layer by heat treatment; and forming a relatively thick fourth insulating layer on the semiconductor substrate. , a step of forming the first, second and third insulating layers, covering the first gate electrode layer and the second mask layer; and reactive ion etching of the first and fourth insulating layers. fifth and sixth insulating layers extending from the fourth insulating layer over the outer sides of the second and third insulating layers and on opposing sides of the second masking layer, respectively; forming a gate insulating layer under the first gate electrode layer and the second, third, fifth and sixth insulating layers from the first insulating layer; an impurity imparting a second conductivity type opposite to the first conductivity type using the second mask layer and the second, third, fifth and sixth insulating layers as masks for the substrate;
forming a source region and a drain region having a first conductivity type in the semiconductor substrate at both positions sandwiching the first gate electrode layer from the upper surface side thereof by ion implantation treatment; , After removing the second mask layer from above the first gate electrode layer, a second mask layer is removed from above the first gate electrode layer, the source ion implantation region, and the drain ion implantation region. A method for manufacturing an MIS field effect transistor, comprising the steps of forming a gate electrode layer, a source electrode layer, and a drain electrode layer, respectively.