JPH0287631A - Manufacture of mis field-effect transistor - Google Patents

Abstract

PURPOSE:To manufacture this transistor whose gate breakdown strength is high, with a good yield and easily by a method wherein a second gate electrode layer, a source electrode layer and a drain electrode layer are formed on a first gate electrode layer, an ion-implanted region for source use and an ion- implanted region for drain use. CONSTITUTION:By an ion implantation treatment of an n-type impurity into a semiconductor substrate 1 by making use of a mask layer 22 and insulating layers 23, 24, a source region 10 and a drain region 11, both of an n-type, are formed, inside the semiconductor substrate 1 from its surface side, in both positions sandwiching a gate electrode layer 5. Then, the mask layer 22 is removed from the upper part of the gate electrode layer 5; after that, a agate electrode layer 12, a source electrode layer 13 and a drain electrode layer 14 are formed on the gate electrode layer 5, the source region 10 and the drain region 11, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an MIS field effect transistor. [Prior Art] Conventionally, a method for manufacturing an MIS field effect transistor has been proposed as described below with reference to FIG. 1. That is, a semiconductor substrate 1 made of, for example, a single crystal 3i and having, for example, n-type is prepared in advance (FIG. 2A). Then, a relatively thin insulating layer 2 made of, for example, SO2 and a conductive layer 3 made of, for example, polycrystalline Si or amorphous Si are sequentially formed on the semiconductor substrate 1 (FIG. 2B). Next, a mask layer 4 made of, for example, photoresist is formed on the conductive layer 3 so as to divide the conductive layer 3 into two when viewed from above (FIG. 2C). Next, by etching the conductive layer 3 using the mask layer 4 as a mask, a gate electrode layer 5 is formed from the IJ conductive layer 1 and below the mask layer 4 (FIG. 2D). Next, mask layer 4 is removed from above gate electrode layer 5 (FIG. 2E). Next, a relatively thick insulating layer 6 made of, for example, SiO2 is deposited on the insulating layer 2, covering the gate electrode layer 5.
form (Fig. 2F). Next, by performing a reactive ion etching process on the insulating layers 6 and 2, insulating layers 7 and 8 are formed extending from the insulating layer 6 onto opposing side surfaces of the gate electrode layer 5, respectively, and the insulating layers 7 and 8 are Then, a gate insulating layer 9 under the gate electrode layer 5 and insulating layers 6 and 7 is formed (FIG. 2G). Next, during ion implantation of n-type impurities into the semiconductor substrate 1 using the gate electrode layer 5 and the insulating layers 7 and 8 as masks, both n-type Forming a source region 10 and a drain region 11 having a mold (FIG. 2H) In this case, the source region 1
0 and the drain region 11 can be obtained as activated ones by performing a heat treatment on the semiconductor substrate 1 during or after the ion implantation process, or can be obtained as activated ones without performing such a heat treatment. Obtained as unactivated. Next, a gate electrode layer 12, a source electrode layer 13, and a drain electrode layer 14 are formed on the electrode layers 1 to 5, the source region 10, and the drain region 11, respectively (Fig. 2).
. In this case, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are replaced by the gate electrode layer 5, the source region 10,
By selectively depositing a metal such as tungsten or molybdenum on the gate electrode FJ5, the source region 10, and the drain region 11, a metal layer made of the above-mentioned metals can be obtained. successively depositing the above-mentioned metal,
Next, by performing heat treatment, the regions of the metal deposited layer on the gate electrode layer 5, the source region 10, and the drain region 11 are made into silicides, and then the regions of the metal deposited layer on the insulating layers 7 and 8 are made into silicides. By removing it by an etching process, a metal silicide layer 1q is formed by siliciding the above-mentioned metal. Further, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are connected to the source region 10 and the drain region 11.
When forming the above-mentioned gold WrS layer from an activated state, there is no particular need for heat treatment of the semiconductor V-plate 1 both during and after the formation of the metal layer, and Gate electrode layer 12, source electrode layer 1
3 and the drain electrode layer 14 are formed as the metal silicide layer described above in a state where the source region 10 and the drain region 11 are activated, heat treatment of the semiconductor substrate 1 is performed when forming the metal silicide layer. Since the metal silicide layer is formed, there is no need to perform any special heat treatment on the semiconductor substrate 1 either during or after the formation of the metal silicide layer.
When the drain electrode layer 14 is formed as the above-mentioned metal layer from a state where the source region 10 and the drain region 11 are not activated, heat treatment is performed on the semiconductor substrate 1 at the time of forming the gold flifl. The source region 1
0 and the drain region 11 are obtained as activated. The above is the conventionally proposed method for manufacturing MIS field effect transistors. MIS type field effect transistor manufactured by the conventional MIS type field effect transistor manufacturing method shown in FIG.
It is clear that the device shown in FIG. 2 (1) functions as a MIS field effect transistor, but the source region 10 and drain region 11 do not use only the gate electrode layer 5 as a mask for the semiconductor substrate 1; Gate electrode layer 5
It is formed by ion implantation of n-type impurities using the gate electrode layer 5 and the insulating layers 7 and 8 as masks, including the insulating layers 7 and 8 formed on opposite sides of the
The source region 10 and the drain region 11 are formed without unnecessarily extending their opposing side ends 1' further inward than below the opposing sides of the electrode layers 1 to 5. Therefore, it functions as a MISIJ field effect transistor with good characteristics. Further, according to the manufacturing method of the MIS type field effect transistor described above in FIG. 2, the source region 10 and the drain region 11
As described above, the opposing side edges of the gate electrode layer 5 can be formed under the opposing sides of the gate electrode layer 5 without unnecessarily extending inward. Effect transistors can be manufactured with good properties. Problem to be Solved by the Invention 1 However, in the case of the conventional manufacturing method of the MIS type field effect transistor shown in FIG. The ions or their radicals pass through the pinholes in the electrode layer 5 to the goo 1 and irradiate the area under the gate electrode layer 5 of the insulating layer 2, so that the gate insulating layer 9 is exposed to pinholes and weak points. Therefore, there is a risk that the gate insulating layer 9 will be formed as having only a low breakdown voltage.
It had a hole that was manufactured with low pressure resistance. Further, by ion implanting n-type impurities into the semiconductor substrate 1 using the gate electrode layer 5 and the insulating layers 7 and 8 as masks, a source region 10 and a drain region 11 are formed into the semiconductor substrate 1 from the upper surface side. After the step of forming (FIG. 2H), a gate electrode layer 12, a source electrode layer 13 are formed on the gate electrode layer 5, the source region 10, and the drain region 11.
and the step of forming the drain electrode layer 14 (second
In Figure ■), a layer made of the material of the gate electrode layer 12 and the source electrode layer 13 is formed on the insulating layer 7.
2 and the source electrode vU13 to short-circuit them, and also on the insulating layer 8, a layer made of the material of the gate electrode layer 12 and the drain electrode layer 14,
There was a fear that the gate electrode layer 12 and the drain electrode layer 14 would be formed in an extended manner so as to short-circuit them. Therefore, there is a fear that MIS type field effect transistors will be manufactured without the function of M[S type field effect transistors. Therefore, the present invention aims to propose a novel MIS type field effect transistor that does not have the above-mentioned drawbacks. (Means for solving the problem) The method for manufacturing the MIS field effect transistor according to the present invention is as follows:
It has the steps described below. That is, (1) forming a relatively thin first insulating layer, a conductive layer, and a nitride layer in that order on a semiconductor substrate having a first conductivity type; ,
A step of forming a first mask layer; and (2) a first etching process for the nitride layer using the first mask layer as a mask, from the nitride to a second etching layer under the first mask layer. A step of forming a mask layer; and (2) a second etching process for the conductive layer using the first and second mask layers as masks, from the conductive layer to the first layer under the second mask layer. (1) removing the seventh mask layer from above the second mask layer, and then using the second mask layer as a mask for the seventh gate electrode layer; forming second and third insulating layers on opposing side surfaces of the first gate electrode layer by heat treatment; (i) forming the second mask layer on the semiconductor substrate; , 5th
and an impurity ion implantation process that gives a second conductivity type opposite to the first conductivity type, using the sixth insulating layer as a mask, into the semiconductor substrate from the upper surface side of the first gate. forming a source region and a drain region having a first conductivity type at both positions sandwiching the electrode layer;
After removing the second mask layer from above the first gate electrode layer, a second mask layer is formed on the M1 gate electrode layer, the source ion implantation region, and the drain ion implantation region.
forming a gate electrode layer, a source electrode layer, and a drain electrode layer, respectively. [Operation/Effect J] MIS' manufactured by the method for manufacturing an MIS type field effect transistor according to the present invention! It is clear that the field effect transistor functions as a MrS type field effect transistor, as in the case of the MIS type field effect transistor manufactured by the conventional MIS type field effect transistor manufacturing method described above in FIG. In addition, since the source region and the drain region are formed according to the conventional MIS type field effect 1 to transistor manufacturing method described above in FIG. The gate electrode layer is formed without unnecessarily extending further inward than below the opposing sides of the gate electrode layer.
It functions as a MIS field effect transistor with good characteristics. Further, according to the method for manufacturing an MIS type field effect transistor according to the present invention, as in the case of the method for manufacturing the conventional MIS type field effect transistor described above in FIG. The opposing side edges of the gate electrode layer can be formed without unnecessarily extending further inward than below the opposing sides of the gate electrode layer.
MIS type field effect transistors can be manufactured with good characteristics. However, in the method for manufacturing an MIS field effect transistor according to the present invention, even if the gel electrode layer has a pinhole, the first insulating layer is not irradiated with the ions or their radicals used in the implantation process, so the gate The insulating layer is formed to have a higher breakdown voltage than that of the conventional MrS field effect transistor described above in FIG. Therefore, a 1Vlrs type field effect transistor can be manufactured with a high gate breakdown voltage. Further, according to the method for manufacturing an MIS field effect transistor according to the present invention, after forming a source region and a drain region in a semiconductor substrate, a layer 1 is formed on the gate electrode, the source region, and the drain region. In the step of forming the gate electrode layer and the drain electrode layer, the gate electrode layer, the source electrode layer, and the drain electrode layer are formed between the gate electrode layer and the source electrode layer, and between the gate electrode layer and the drain electrode layer. There is a risk of short-circuiting between the 12i layers.
This is much less than the conventional manufacturing method of MIS type field effect transistors described above in the figure, and therefore MIS type field effect transistors can be easily manufactured with high yield.
I can do that. [Example 1] Next, MI' according to the first invention of the present application with reference to FIG.
An example of the manufacturing method of S-type field effect 1 - transistor will be described. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The method for manufacturing the MIS field effect transistor according to the first invention of the present application shown in FIG. 1 includes the following sequential steps. That is, the conventional MfS type field effect 1 described above in FIG.
~Similar to the manufacturing method of transistors, for example, single crystal Si
A semiconductor substrate 1 having, for example, n-type is prepared in advance (FIG. 1A). Then, on the semiconductor substrate 1, a relatively thin insulating layer 2 made of, for example, SO2, a conductive layer 3 made of, for example, polycrystalline Si or amorphous 3i, and a nitride layer 21 made of, for example, silicon nitride, are formed. They are formed one after another (FIG. 1B). Next, a mask layer 4 made of, for example, photoresist is formed on the nitride layer 21 so as to divide the conductive layer 3 into two when viewed from above (FIG. 1C). By etching using the mask layer 4 as a mask,
From the nitride layer 21 a further mask layer 22 under the mask layer 4 is formed (FIG. 1D). Next, by etching the conductive layer 3 using the mask layers 4 and 22 as masks, the conductive layer 3 to 1 and the gate electrode layer 5 under the mask layer 22 are formed (first
Figure E). Next, mask layer 4 is removed from above gate electrode layer 5 (FIG. 1F). Next, insulating layers 23 and 24 are formed on opposing side surfaces of the gate electrode layer 5 by heat treatment using the mask layer 22 as a mask. (FIG. 1G) Next, by ion-implanting n-type impurities into the semiconductor substrate 1 using the mask layer 22 and the insulating layers 23 and 24 as masks, a gate electrode is implanted into the semiconductor substrate 1 from the upper surface side. A source region 10 and a drain region 11, both of n-type, are formed at both positions with the layer 5 in between. In this case, the source region 10 and the drain region 11 are obtained as activated ones by subjecting the semiconductor substrate 1 to heat treatment during or after the ion implantation process, or by such heat treatment. It is obtained as a substantially unactivated product without any treatment. Next, after removing the mask layer 22 from above the glue electrode layer 5, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are formed on the gate electrode layer 5, the source region 10, and the drain region 11. (Fig. 1J). In this case, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are replaced by the gate electrode layer 5, the source region 10,
By selectively depositing a metal such as tungsten or molybdenum on the gate electrode layer 5, the source region 10, and the drain region 11, the gate electrode layer 5, the source region 10, and the drain region I411 can be obtained by selectively depositing a metal such as tungsten or molybdenum on the gate electrode layer 5, the source region 10, and the drain region I411. successively depositing the metal described above,
Next, heat treatment is applied to the metal deposited layer 1, electrode layer 5, source die iii! 10 and drain region 11
The upper region is silicided, and then the region on the insulating layers 7 and 8 of the metal 1 stack is removed by etching to obtain a metal silicide layer in which the above-mentioned metal is silicided. The electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are connected to the source region 10 and the drain region 11.
When forming the above-mentioned metal layer from an activated state, there is no need to perform special heat treatment on the semiconductor IS board 1 both during and after the formation of the metal layer, and the gate voltage i layer 12, source electrode layer 13
When the drain electrode layer 14 is formed as the metal silicide layer described above in a state where the source region 10 and drain region 11 are activated, heat treatment is performed on the semiconductor substrate 1 when forming the metal silicide layer. Therefore, there is no need to perform special heat treatment on the semiconductor substrate 1 both during and after the formation of the metal silicide layer. When the drain region 11 is formed as the above-mentioned metal layer from an unactivated state, the semiconductor substrate 1 may be subjected to heat treatment at the time of forming the metal layer, or after the metal layer is formed. By performing heat treatment on the semiconductor substrate 1, the source region 10 and the drain region 11 are activated. The above is an embodiment of the method for manufacturing an MIS field effect transistor according to the present invention. According to the embodiment of the method for manufacturing the MIS type field effect 1-transistor according to the present invention, it is clear from what has been described in the [Operations and Effects] section, so detailed explanation will be omitted, but (Operations and Effects) The excellent effects described in section 1 are obtained by 1q.In the case of the manufacturing method of MIS type field effect 1 to transistor according to the present invention, when forming the insulating layers 23 and 24, the thickness can be increased as desired. Therefore, the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 can be formed more easily without the risk of short-circuiting. This is merely one embodiment of an effect transistor, and various modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a line cross-sectional view of sequential steps showing an embodiment of a method for manufacturing a MIS type field effect transistor according to the first invention of the present application. FIG. 3 is a cross-sectional view showing sequential steps in a conventional MIS field effect transistor manufacturing method. 1... Semiconductor substrate 2... Insulating layer 3... Conductive layer 4... Mask layer 5 ......Gate electrode layer 6...Insulating layer 7...Insulating layer 8...Insulating layer 9 ......Gate insulating layer 10...Source electrode layer 11...Drain region 12...Gate electrode layer 13 ......Source electrode layer 14...Drain electrode Fi layer 21...
...Nitride layer 22 ...Mask layers 23, 24 ...Insulating layer Fig. 1

Claims (1)

[Claims] 1. A step of sequentially forming a relatively thin first insulating layer, a conductive layer, and a nitride layer in that order on a semiconductor substrate having a first conductivity type; A step of forming a first mask layer on the nitride layer, and a first etching treatment of the nitride layer using the first mask layer as a mask, from the nitride to the first mask layer. The second mask layer is removed from the conductive layer by a step of forming a second mask layer under the mask layer, and a second etching treatment for the conductive layer using the first and second mask layers as masks. forming a first gate electrode layer under the mask layer; and after removing the first mask layer from above the second mask layer, applying the second mask to the first gate electrode layer; forming second and third insulating layers on opposing side surfaces of the first gate electrode layer by heat treatment using the layers as masks; By ion implantation of an impurity that provides a second conductivity type opposite to the first conductivity type using the second and third insulating layers as masks, from the upper surface side of the semiconductor substrate,
At both positions sandwiching the first gate electrode layer, the first
forming a source region and a drain region having a conductivity type of; and after removing the second mask layer from above the first gate electrode body, forming the first gate electrode layer and the source ion. A method for manufacturing an MIS field effect transistor, comprising the steps of forming a second gate electrode layer, a source electrode layer, and a drain electrode layer on the implantation region and the drain ion implantation region, respectively.