JPH0287674A - surge protection circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a surge protection circuit for protecting internal circuits from surges in a semiconductor integrated circuit device.

(Prior Art) In a semiconductor integrated circuit device, a surge protection circuit is usually provided in an input/output section. A PN junction or MO is used in the surge protection circuit.
An S transistor is provided, and the protection element is activated when the voltage at the input/output section exceeds the forward voltage of the PN junction or the punch-through m voltage of the MOS transistor from the range of the circuit power supply.

FIG. 7 shows an example of a protection circuit using the forward voltage Vbc of a PN junction, and FIG. 8 shows a cross-sectional view of the device.

A resistor 3 is connected between the internal circuit 2 and the input/output pad 1, and as a protection circuit, a diode 4 is connected between the high voltage power supply V+ and a diode 5 is connected between the low voltage power supply V-. ing.

In the circuit of FIG. 7, when the voltage applied to the input/output pad 1 exceeds the forward voltage Vbe of the PN junction from the circuit power supply range (v4 to V-), the protection element 4 or.

5 is activated and clamped at that voltage. The input/output voltage range in which the protection element does not work is (V"+Vbe=V--Vbe
). Generally Vbe=0.6-0.7V.

Figure 9 shows the punch-through voltage B of the NMOS transistor 6.
This is a protection circuit that utilizes Vds and the forward voltage Vbe of the PN junction. FIG. 10 shows an example of the device, in which the resistor 3 is formed of a polysilicon layer.

In the protection circuit shown in FIG. 9, if the voltage applied to the input/output pad 1 exceeds the punch-through voltage from the source voltage V- of the NMOS transistor 6 on the high voltage side, the NMOS transistor on the low voltage side
When the substrate voltage of the transistor 6 exceeds the forward voltage of the PN junction, it is clamped at that voltage. Therefore, in the protection circuit of FIG. 9, the input/output voltage range in which the protection element 6 does not work is (V-+BVds"V--Vbe)'T! Generally, Bvds is 10 to 2 ov.

(Problem to be Solved by the Invention) In the protection circuit shown in Figure 7 or Figure 9, the voltage range in which the protection element does not operate is narrow, and it cannot be used if the input/output voltage exceeds that range in normal operating conditions. .

An object of the present invention is to provide a surge protection circuit in which the range in which the protection element does not operate is wide and the range can be easily changed.

(Means for Solving the Problems) The surge protection circuit of the present invention includes at least two PN junctions connected in series in different directions, one end of which is connected to an input/output pad, and the other end of which is connected to a power supply or ground. connected to.

(Function) When the surge protection circuit includes only two PN junction series circuits, if the other end is connected to the low voltage power supply ■-, the voltage applied to the input/output terminal will be (V-+ B Ve
It is clamped when it becomes higher than b+Vbe).

In addition, when the other end is connected to the high voltage side power supply V+, the voltage applied to the input/output terminal is (V''-B Veb-Vbe
) will be clamped when lower. BVeb is P
This is the breakdown voltage in the reverse direction of the N junction, which is higher than the forward voltage Vbe of the PN junction, and the unclamped input/output voltage range is wide.

By further adding a PN junction to a series circuit including a pair of PN junctions in opposite directions, it is possible to widen the voltage range over which the input and output voltages are clamped.

(Example) FIG. 1 represents one embodiment.

A high voltage power supply V" is connected between the input/output pad 1 and the internal circuit 2.
Two PN junctions 11.12 with mutually opposite directions are connected in series between both, and two PN junctions 13.14 with mutually opposite directions are connected in series between the low voltage power supply V-. ing.

FIG. 2 represents an apparatus for realizing the embodiment of FIG.

15 is a P-silicon substrate; 16 is an N-well diffusion or N-epitaxial layer formed on the substrate 15; P
To form N junctions 11-14.

P+ diffusion layers 17, 18, and 19 are formed in the well 16, and N4 diffusions !20, 21, 22, and 23 are formed inside these P" diffusions @17, 18.19. P" diffusion layers 17 and the N+ diffusion WJ2o constitute a PN junction 11, and the P" diffusion layer 18 and the N4 diffusion layer 21 constitute a PN junction 11.
Junction 12 is configured, P44 diffusion 18 and N0 diffusion layer 22
The PN junction 13 is constructed by the P00 diffusion 19 and the N
A PN junction 14 is configured by the zero diffusion Wj23.

Each PN junction 11 to 14 is an insulating film 2 formed on the substrate surface.
They are connected by metal wiring 25 through contact holes 4 to form the circuit shown in FIG.

The N-well 16 is separated by a P'' diffusion layer 26, and the N'''' well 16 is placed in a floating state so that no charge flows from the P00 diffusions 17-19.

FIG. 3 shows another embodiment, in which the PN junctions of the protection circuit of FIG. 1 are replaced.

FIG. 4 shows a device for realizing the circuit of FIG. 3, in which 15 is a substrate, 16 is an N-well diffusion or N-epitaxial layer, 27.28 is a P'' diffusion layer, and 29 to 32 are N1 diffusion layers. The P11 diffusion 27 and the N+ diffusion layer 29
An N junction 12a is configured, a PN junction 11a is configured by the P00 diffusion 27 and the N0 diffusion layer 30, and the P0 diffusion W!
j28 and the N0 diffusion layer 31 constitute a PN junction 14a, and the P+ diffusion layer 28 and the N2 diffusion layer 32 constitute a PN junction 13a. Each PN junction 11a to 14a
are connected by metal wiring 33 through contact holes in an insulating film 24 formed on the surface of the substrate so as to form the circuit shown in FIG.

In the embodiments shown in FIGS. 1 and 3, the input/output voltage range in which the protection element does not work is (V-+BVe
b + Vbs) ”-・(1), and for the low voltage side (V” −B Veb −Vbe) ...”・(
2). - For example, V'=5V, V-=GND,
When Vbe=0.6V and BVeb=7.4V, the input/output voltage range of the protection element is from -3V to 8V from equations (1) and (2) above.

In the embodiment, a pair of PN junctions are provided between the input/output pad 1 and the power supplies v" and v-, but in order to further widen the voltage range in which the protection element does not work, an additional PN junction is added to the series circuit of the pair of PN junctions. A PN junction may be connected.

In the embodiment, protection circuits are also provided both between the input/output pad 1 and the high voltage power supply V-, and between the input/output pad 1 and the low voltage power supply V-. If it is clear that only one of them is applied, the protection circuit may be provided only on either the high voltage power supply side or the low voltage power supply side.

One output pad 1 and internal circuit 2 to enhance protection function
A resistance may be added between the two.

Next, an example of a circuit convenient for using the protection circuit of the embodiment is shown in FIG.

FIG. 5 shows an oscillation circuit whose frequency is determined by a resistor 40 and a capacitor 41. 42 and 43 are inverters, a region 44 surrounded by broken lines is a semiconductor integrated circuit, and a capacitor 41 is externally attached. It is assumed that a protection circuit as shown in the embodiment is incorporated in each of the A and B terminals.

The operation shown in FIG. 5 is shown in FIG.

Vthl is the threshold voltage of the inverter 42.

Va is the potential of the A terminal, and vb is the potential of the B terminal.

In the cono circuit, V"=5V, V-=GND, Vthl=2.
5V, the amplitude range of the potential vb of the B terminal = -2, 5
~7.5v.

If the surge protection circuit in the oscillation circuit shown in Figure 5 is
When the conventional protection circuit shown in the figure is used, current flows through the protection element of the B terminal, causing the power supply current to increase and the oscillation frequency to change from its theoretical value. On the other hand, Figure 1 or 3
When the protection circuit shown in the figure is used, no current flows through the protection element in the oscillation circuit of FIG. 5, and the oscillation circuit operates normally according to its theoretical value.

(Effects of the Invention) The protection circuit of the present invention includes at least two P'N junctions connected in series in different directions, one end of which is connected to an input/output pad, and the other end of which is connected to a power supply or ground. Therefore, it is possible to set a wide voltage range in which the protection circuit does not operate for input/output voltages exceeding the voltage range.

Moreover, it is also easy to change the voltage range. Therefore, current consumption and malfunctions can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment, FIG. 2 is a sectional view showing the device of the same embodiment, FIG. 3 is a circuit diagram showing another embodiment, and FIG. 4 is a circuit diagram of the embodiment shown in FIG. 5 is a circuit diagram showing an example of an oscillation circuit suitable for using the protection circuit of the embodiment, FIG. 6 is a waveform diagram showing the operation of the oscillation circuit of FIG. 5, and FIG. 7 is a sectional view showing the device. is a circuit diagram showing an example of a conventional protection circuit, FIG. 8 is a sectional view showing the device, FIG. 9 is a circuit diagram showing an example of another conventional protection circuit, and FIG. 10 is a sectional view showing the device. It is. 1... Input/output pad, 2... Internal circuit, 11 to 14. 11a to 14a-PN junction.

Claims (1)

[Claims] (1) Two PNs connected in series with mutually different directions
A surge protection circuit that includes at least a junction, one end connected to an input/output pad, and the other end connected to a power supply or ground.