JPH0287715A - Output circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for connecting a load resistor at the test use by connecting P, W channel transistors(TRs) between a power supply and ground and using the P-channel TR switchingly. CONSTITUTION:The sources of the P, N-channel MOS TRs 4, 1 whose drains are connected together are connected to a power supply VDD and ground, the TR 4 is turned on by using a test signal via an inverter 5 and an OR gate 6 only at the test and the TR 4 is connected to the TR 1 as a load resistor, and only the TR 1 is used normally and an output signal is extracted from an output terminal 2 connecting to the drain of the TR 4 in response to the input signal. Through the constitution above, an output circuit not requiring to connect the load resistor at the test is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to an open drain type output circuit.

[Conventional technology]

Conventionally, this type of output circuit is composed of only an N-channel MOS transistor 1, as shown in FIG. This is an output circuit with no load resistance or load resistance.

This open drain output circuit is convenient and widely used because it can be used by directly connecting the output terminals of a plurality of oven train output circuits as shown in FIG. Note that in the figure, 3 is a load resistor connected between the power supply terminal VDD and the output terminal.

Also, when testing an open drain output circuit, in order to operate it functionally, it is necessary to connect a load resistor 3 between the output terminal 2 and the power supply terminal VDD as shown in FIG. In particular, functionally, when the input signal is "0", the N-channel MO9) transistor 1 is turned off, so the output terminal 2 outputs the power supply terminal V00 level "1" when the input signal is "1".
At this time, the N-channel MOS transistor 1 is turned on, rQJ at the ground terminal GND level is output, and it operates as an inverter that inverts the input signal.

[Problem to be solved by the invention]

The conventional output circuit described above is inconvenient because it is necessary to connect a load resistor even during test use. Furthermore, when performing tests from 1 onwards using an LSI tester, the resistance value is often fixed at a constant value due to the measurement jig, and if a large resistance value is used, there are drawbacks such as the inability to perform high-speed tests. Ta.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned point '', and is to provide an output circuit that does not require a load resistor during test use.

[Means to solve the problem]

The output circuit of the present invention uses a P-channel MOS transistor as a load, and functions as an open-drain output circuit by always turning off this P-channel MOS transistor during normal use.
The OS transistor has switching means to function as a load.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, 4 is a P-channel MOS transistor, and 5 is a P-channel MOS transistor.
is an inverter, and 6 is an OR gate.

So to explain the operation, during normal use the test signal is r□
, so the output of the inverter 5 becomes "1" and the output of the OR gate 6 also becomes "1", the P-channel MOS transistor is turned off, and only the N-channel MOS transistor l functions as a normal oven drain circuit that receives the input signal. do. Further, during testing, since the test signal becomes "1", the output of the inverter 5 becomes r□, and the input signal is also applied to the gate of the P-channel MOS transistor 4 through the OR gate 6. That is, during testing, the N-channel MOS transistor 1 and the P-channel MOS transistor 4 constitute an inverter, which functions as an output circuit that inverts an input signal.

〔Effect of the invention〕

As explained above, the output circuit of the present invention is a P-channel MO
When using the S transistor as a load, it functions as a normal oven drain output circuit by turning it off at all times during normal use, and functions as an inverter together with the N channel MOS transistor during test use, so it is necessary to connect a load resistor for measurement. It has the effect of being convenient to use without any problems.

Busu F issue

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional example, and Figs. 3 and 4 show first and second usage examples of a conventional output circuit. It is a circuit diagram. 1.11,12. IN...N channel MOS transistor, 2, 21, 22.2N...Output terminal, 3...
Load resistance, S...P channel MOS transistor, 5
...Inverter, 6...Or gate.

Claims (1)

[Claims] In an output circuit in which the sources of a P-channel MOS transistor and an N-channel MOS transistor are connected to a power supply terminal and a ground terminal, respectively, and their respective drains are connected in common to form an output terminal, are the transistors driven by both transistors, or the An output circuit comprising means for switching whether to drive only the N-channel transistor by always turning off the P-channel MOS transistor.