JPH0288979A - Logic circuit of scanning system - Google Patents

Abstract

PURPOSE:To constitute a logic circuit of a scanning system without increasing the number of scanned data output terminals by constituting the logic circuit in such way that scan-in/scan-out can be performed between flip flops respectively provided with scan access terminals and data output terminals of scan lines can also work as output terminals other than bi-directional terminals. CONSTITUTION:A flip flop SFF3, the output of which is directly connected with an external terminal, is positioned to the final stage of scan lines. When such flip flop does not exist on a scan line, a flip flop SFF9 for scanning is inserted between a combination circuit 6 and output terminal DO4. Therefore, a scan data output terminal can also work as an ordinary data output terminals. Therefore, a logic circuit of a scanning system can be realized without increasing the number of pins as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to scan logic circuits including combinational circuits and sequential circuits.

BACKGROUND OF THE INVENTION In recent years, with the development of integrated circuit technology, logic circuits have become larger in scale, and complex logic functions have become more densely integrated. On the other hand, fault testing for logic circuits is extremely difficult and time-consuming, so how to efficiently create test patterns with a high fault inspection rate in a short period of time, that is, how to shorten test time, has become an important issue.

Conventionally, a scanning method has been used as an effective means for this test. With the scan method, sequential circuits can be converted into combinational circuits for testing, making it possible to significantly shorten test time.

FIG. 3 is a logic circuit diagram using the conventional scan method. 3 is a first scan block, 2 is a second scan block, 3 is a combinational circuit, and 4 is a scan line, which are each represented by a thick solid line. SFF 1 to 8 are flip 70 blocks for scan testing, N/T is a switching signal input terminal for scan testing and normal operation, and CLK is basically a switching signal input terminal. SI1~2 are scan data input terminals, 801~2 are scan data output terminals,
D11-4 are normal data input terminals, and DO1-4 are normal data output terminals.

Figure 4 shows the flip-flop 5FFI for scan test.
8 is an individual internal circuit diagram. D is the data input terminal during normal operation, DT is the data input terminal during scan test,
Q is a data output terminal. N/T and CLK are the same as described in FIG. 7 is a normal 1 scan mode switching circuit, which connects the control signal terminal SE through the input terminal N/T.
When "H' is inputted from L, data from data input terminal A is selected. On the other hand, when L' is inputted to input terminal N/T, data from data input terminal B is selected. 8 is a D-type flip 70 tube.

In FIG. 4, when the scan mode switching signal of the input terminal N/T is set to "H", the scan data of the input terminal DT becomes the input signal of the D-type flip-flop 8, and the Q terminal is input according to the basic clock signal of the clock input terminal CLK. The scan data will be output.

In FIG. 3, the data output terminals Q of the scan test flip-flops 5FFI to 4 and 5FF5 to 8 are connected to the scan data input terminals DT, and the scan line 4 is
shall be. First, input the high level signal I Hl to the N/T terminal, and input the basic clock from the CL K terminal.
The scan data of Sll-2 is sent to each data output terminal Q of the scan test flip-flops 5FFI and 5FF5.
is set to When you enter the next basic clock.

The next scan data from the Sll~2 terminal is set to 5FFI and 5FF5, and the previous data is set to 5FF2 and 5FF.
Set to 6. Similarly, when the basic clock from the CLK terminal is input, the scan data of the S11-2 terminals becomes 5FF.
It is set in order to I-4 and 5FF5-8. In this state, L' is input to the N/T terminal to change each flip-flop from scan mode to normal operation. Furthermore, input signals to the combinational circuit 3 are set from the D11 to D4 terminals, and one basic tarok is input from the CLK terminal.

As a result, the circuit operates, and the operation results are output to the flip-flops of 5FF1-8 and the terminals D01-4.

Here, input "H" again from the N/T terminal to return each flip-flop to the scan mode.Furthermore, Sll-2
Therefore, in the same manner as described above, new data to be set in each flip-flop is input in sequence, and new data is set in 5FFI to 8. Further, along with this data setting, the data after the circuit operation of 5FFI to 4 is output to the Sol terminal, and the data after the circuit operation of 5FF5 to 8 is output to the SO2 terminal together with the data shift.

In this way, in a scan type logic circuit, arbitrary data can be set in or retrieved from flip-flops in the circuit using scan lines, and a synchronous sequential circuit can be treated as a combinational circuit.

Problems to be Solved by the Invention However, in the above configuration, the scan data input terminal can be used commonly as an input terminal, but the scan data output terminal cannot be used also, so a scan data output terminal is required corresponding to the scan line. The total number of bins increases.

The present invention solves the above problems, and aims to provide a scan type logic circuit without increasing the number of scan data output terminals.

Means for Solving the Problems In order to achieve this object, the scan type logic circuit of the present invention uses a shift type between flip-flops having scan access terminals in a logic circuit including a synchronous sequential circuit in addition to a combinational circuit. The present invention has a configuration in which scan-in and scan-out are performed by using a scan line, and a configuration in which the data output terminal of the scan line is also used as an output terminal other than a bidirectional terminal.

Effect: With the above configuration, a scan type logic circuit can be configured without increasing the number of scan data output terminals in a logic circuit including a sequential circuit.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of a scan type logic circuit in one embodiment of the present invention. DO3 and DO4 are normal data and scan data output terminals, and 5FF9 is a scan test flip-flop. In addition, 1 is a first scan block, 2 is a second scan block, 3 is a combinational circuit, 4 is a scan line, 5FFI to 8 are flip 70 blocks for scan test, and N/T
The terminals, CLK terminal, and D11 to D4 terminals have the same structure as the conventional example.

In the first block 1, 5
FFI4 constitutes a scan line, but this is a case where there is a scan flip-flop 5FF3 whose output is directly connected to an external terminal.

5FF3 instead of 5FF4 at the last stage of the scan line
, the output Q of the flip-flop is directly connected to the external terminal DO2, so it can be used as both the scan data output terminal and the normal data output terminal. By doing so, scan data is output to the D02 terminal in the scan mode, and normal data is output in the normal operation.

In the second block 2, 5FF is used as in the conventional diagram of FIG.
5 to 8 constitute a scan line, but this is a case where there is no scan flip-flop whose output is directly connected to an external terminal like in the first block 1.

As shown in FIG. 2, assuming that 5FF8 is connected to the normal data output terminal DO4 via the combinational circuit 5, a scan flip-flop 5FF9 is inserted between the final stage gate 6 of the combinational circuit and the DO4 terminal, 5FF8
The output Q of the FF9 is connected to the scan data input DT of the 5FF9 to generate a scan line. Further, the N/T and CLK inputs connect respective corresponding input lines of 5FF8.

When summarized in the overall diagram, as shown in Figure 1, 5FF5 to 5
FF9 constitutes scan line 4, and the output of 5FF9 is directly connected to external terminal DO4, and the first block 1
Similarly, the D○4 terminal can also be used as the scan data output terminal.

However, in this case, since one flip-flop is inserted, data is output from the DO4 terminal with a delay of one basic tarok during normal operation and scan mode.

Effects of the Invention The present invention provides a flip-flop whose output is directly connected to an external terminal by arranging it at the final stage of the scan line. By inserting a scan flip-flop between the combinational circuit and the output terminal, the scan data output terminal can be used as the normal data output terminal, realizing a scan type logic circuit without increasing the overall number of bins. It is something.

[Brief explanation of the drawing]

FIG. 1 is a scan method logic circuit diagram according to an embodiment of the present invention, FIG. 2 is a circuit diagram after inserting a flip-flop, FIG. 3 is a conventional scan method logic circuit diagram, and FIG. 4 is a diagram of a scan flip-flop SFF. It is an internal circuit diagram. 1...First scan block, 2...
・Second scan block, 3...Combination circuit, 4...Scan line, 5...
Combinational circuit, 6... Combinational circuit final stage gate, 7... Normal/scan mode switching circuit, 8... D-type flip-flop. Name of agent: Patent attorney Shigetaka Awano and 1 other person! ...-8
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Claims (1)

[Claims] In a logic circuit including sequential circuits (flip-flops, etc.) in addition to combinational circuits, a means for performing scan-in/scan-out between flip-flops (scan test flip-flops) having scan access terminals by a shift method, and a scan line A scan type logic circuit having a configuration in which a data output terminal also serves as an output terminal other than a bidirectional terminal.