JPS6236573A - Clock signal input system - Google Patents

Abstract

PURPOSE:To enable the implementation of a scanning test operation accuracy, by providing a gate in a receiving route for clock signals for normal operation to cut off the gate before a clock signal for scanning test is inputted. CONSTITUTION:In the normal operation, the clock signal (tck) for a test is set at the logical '0'. As a result, the output signal (q) of an FF1 to be inputted into an input terminal A of a gate 4 is outputted to an output terminal C as intact and transmitted to a clock terminal CK of an FF3. When a scanning test is carried out, by signal (tck) is set at the logical '1'. Consequently, the clock signal (ck) to be transmitted to the clock terminal CK of the FF3 from the output terminal C of the gate 4 is also set at the logical '1' regardless of the logical value of the output signal (q) of the FF1. Under such a condition, when a scanning data signal (sd) is inputted into a scanning data terminal SD of the FF1 while a scanning clock signal (sck) is inputted into each of the FFs 1-3, the scanning data signal (sd) is transferred through the FFs 1-3 synchronizing the scanning clock signal (sck).

Description

[Detailed Description of the Invention] [Summary] A gate is provided in the clock signal reception path of an integrated circuit that receives an output signal from another integrated circuit as a clock signal for normal operation, and a clock signal for scanning test is input to the integrated circuit. By blocking the gate during the test, the scanning test can be performed reliably.

[Industrial application field]

The present invention relates to improvements in clock signal input methods in integrated circuits.

For example, in semiconductor integrated circuits that constitute flip-flop circuits, in addition to the terminals that receive clock signals and data signals for normal logic operations, test data is circulated between similar semiconductor integrated circuits connected in cascade. let,
It has terminals for receiving clock signals and data signals for so-called scanning tests. Only one of the clock signal and data signal for normal operation and the clock signal and data signal for scanning test can be input at the same time.

Note that some integrated circuits receive an output signal from another integrated circuit as a clock signal for normal operation.

Even in this type of integrated circuit, it is desired that the scanning test be performed reliably.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional clock signal input method.

In FIG. 3, three flip-flops 1.2 and 3 are interconnected.

Each of the flip-flops 1 to 3 has a clock terminal CK and a data terminal that receive a clock signal ck and a data signal d for normal operation, and a scan clock terminal that receives a scan clock signal sck and a scan data signal sd for a scan test, respectively. a terminal SCK and a scan data terminal SD;
It is provided with an output terminal Q that sends out an output signal q. When the clock signal ck and the data signal d are respectively input to the clock terminal CK and the data terminal of each flip-flop 1 to 3, the scanning clock terminal SCK
and prohibits input of scan clock signal sck and scan data signal sd to scan data terminal SD, and when scan clock signal sck and scan data signal sd are input to scan clock terminal SCK and scan data terminal SD, clock Consideration must be taken to prohibit input of the clock signal ck and data signal d to the terminal CK and data terminal, respectively.

Note that the clock terminal GK of the flip-flop 3 receives the output signal q sent from the output terminal Q of the flip-flop 1.
is input as the clock signal ck.

In addition, the scanning data terminals SD of flip-flops 2 and 3
are input with output signals q output from output terminals Q of flip-flops 1 and 2, respectively.

When performing a scan test on flip-flops 1 to 3,
A scan data signal sd is input to the scan data terminal SD of the flip-flop 1, and a scan clock signal sck is input to the scan clock terminal SCK of each of the flip-flops 1 to 3. As a result, the scanning data terminal SD of flip-flop I
The scan data signal sd input to the flip-flops 2 and 3 is sequentially transferred to flip-flops 2 and 3 in synchronization with the scan clock signal sck.

However, even during the scan test, the output signal q output from the flip-flop 1 is input as the clock signal ck to the clock terminal GK of the flip-flop 3, so the scan test is not performed for the flip-flop 3. It becomes possible.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional clock signal input method, the flip-flop 3 receives the output signal q of the flip-flop 1 at the clock terminal GK even during the scan test, which makes it impossible to perform the scan test. was there.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, in an integrated circuit 20 that receives an output signal q from another integrated circuit 10 as a clock signal ck for normal operation and also receives a clock signal sck for a scan test, a signal is connected to the reception path of the clock signal ck. A gate 30 is provided to send a clock signal sck for scanning test to other integrated circuits 10.
At the same time, when using manual power, the gate 30 is set to a blocked state.

[Effect]

That is, according to the present invention, when a clock signal for a scan test is input to an integrated circuit, output signals from other integrated circuits are not input as clock signals, and a scan test operation can be performed reliably.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a clock signal input method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, there is a connection between the output terminal Q of the flip-flop 1 and the clock terminal CK of the flip-flop 3.
A gate 4 is provided. One input terminal A of the gate 4 receives the output signal q sent from the output terminal Q of the flip-flop 1, and the other input terminal B receives the test clock signal tck.

During normal operation, the test clock signal tck is logic “0”
is set to As a result, the output signal q of the flip-flop 1 inputted to the input terminal A of the gate 4 is outputted to its side output terminal C, and the output signal q of the flip-flop 1 is inputted to the input terminal A of the gate 4.
It is transmitted to K.

As a result, flip-flop 3 performs normal operation as in FIG.

When performing a scan test next, test clock signal tC
Set k to logic "1". As a result, the clock signal ck transmitted from the output terminal C of the gate 4 to the clock terminal CK of the flip-flop 3 is also set to logic "1" regardless of the logic value of the output signal q of the flip-flop 1.

In this state, the scan data terminal SD of flip-flop 1
The scanning data signal sd is input to each flip-flop l.
When the scanning clock signal sck is input to the flip-flops 1 to 3, the scanning data signal sd is sequentially transferred through the flip-flops 1 to 3 in synchronization with the scanning clock signal sck.

During this time, the output signal q output from the output terminal Q of the flip-flop 1 is sent to the clock terminal C of the flip-flop 7.
K is never input, and the flip-flop 3 reliably performs the scan test operation.

On the other hand, when normal operation and scanning test operation are not performed, the test clock signal tc of the required period is applied to the input terminal B of the gate 4.
When inputting k, clock terminal C of flip-flop 3
A test clock signal tck is input to K via a gate 4, and the flip-flop 3 is operated on a test basis.

As is clear from the above description, according to this embodiment, the gate 4 is inserted between the output terminal Q of the flip-flop 1 and the clock terminal CK of the flip-flop 3, and the gate 4 is turned on and off by the test clock signal tck. By controlling this, normal operation and scanning test operation can be carried out reliably. It is also possible to test the flip-flop 3 alone using the test clock signal tck.

Note that FIG. 2 is only one embodiment of the present invention, and the integrated circuit is not limited to a flip-flop, for example, and many other modifications may be considered, but the present invention will not apply in any case. The effect remains unchanged.

〔Effect of the invention〕

As described above, according to the present invention, when a clock signal for a scan test is input to an integrated circuit, output signals of other integrated circuits are not input as a clock signal, and a scan test operation can be reliably performed. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a clock signal input method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional clock signal input method. In the figure, ■ to 3 are flip-flops, 4 and 3 are flip-flops,
0 is a gate, 0 and 2o are integrated circuits, ck is a clock signal, d is a data signal, q is an output signal, sck is a scanning clock signal, sd is a scanning data signal, and tck is a test clock signal. ,! Planning, kite counterfeit map hi 15 ding L door] East geese e 1 - Ω 勺口, nofi word name Xf 1 chibe η 2
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Claims (1)

[Claims] An integrated circuit (20) that receives an output signal (q) of another integrated circuit (10) as a clock signal (ck) for normal operation and also receives a clock signal (sck) for scanning test. ), a gate (30) is provided in the receiving path of the clock signal (ck).
A clock signal input method, characterized in that the gate (30) is set to a cut-off state when the clock signal (sck) for scanning test is input together with the other integrated circuit (10).