JPH03104149A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH03104149A
JPH03104149A JP1240716A JP24071689A JPH03104149A JP H03104149 A JPH03104149 A JP H03104149A JP 1240716 A JP1240716 A JP 1240716A JP 24071689 A JP24071689 A JP 24071689A JP H03104149 A JPH03104149 A JP H03104149A
Authority
JP
Japan
Prior art keywords
leads
pins
printed board
pin
corners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1240716A
Other languages
Japanese (ja)
Inventor
Takehisa Tsujimura
辻村 剛久
Masahiro Sugimoto
杉本 正浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1240716A priority Critical patent/JPH03104149A/en
Publication of JPH03104149A publication Critical patent/JPH03104149A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate registration at the time of mounting on a printed board, by arranging register pins at positions separated from leads a specified distance apart, which leads are positioned at two diagonal corners of leads arranged in a matrix type. CONSTITUTION:Many pin leads 2 connecting electrodes of a semiconductor chip with the outside are arranged in a matrix type on the lower surface of a package main body 1. Register pins 3 longer than the leads 2 are arranged at four corners of the leads 2, so as to have the same pitch as the pitch P of the leads 2 on the diagonal corners. The positions of the lead pins 3 have the same pitch as the leads 2, but the pins 3 have no adjacent pins, so that the pin 3 is positioned from the nearest lead 2 2<1/2>XP apart. Positioning through holes for mounting can be arranged with the above pitch, so that the pins 3 are inserted into the through holes and the registration to the printed board is facilitated at the time of mounting on a printed board.

Description

【発明の詳細な説明】 〔概 要〕 半導体装置の表面実装型のピングリッドアレイパッケー
ジに関し、 表面実装時の位置合わせを容易とすることを目的とし、 パッケージ裏面に多数のピン状リードが所定のピッチで
マトリクス状に配設された表面実装型のピングリッドア
レイパッケージにおいて、上記マトリクス状に配置され
たリードの四隅の少なくとも対角の二つの隅の該リード
から該所定のピッチより長い距離を隔てた位置に該リー
ドより長さの長い位置合わせ用のピンを設けるように構
成する。
[Detailed Description of the Invention] [Summary] Regarding a surface-mounted pin grid array package for a semiconductor device, a large number of pin-like leads are arranged in a predetermined position on the back surface of the package in order to facilitate alignment during surface mounting. In a surface mount type pin grid array package arranged in a matrix with a pitch, at least two diagonal corners of the four corners of the leads arranged in the matrix are spaced apart from the leads by a distance longer than the predetermined pitch. A positioning pin having a longer length than the lead is provided at the position shown in FIG.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の表面実装型のピングリッドアレイ
パッケージに関する。
The present invention relates to a surface-mounted pin grid array package for semiconductor devices.

〔従来の技術〕[Conventional technology]

第4図は従来のピングリッドアレイパッケージの1例を
示す図である。これはセラくツク等のパッケージ本体1
の中に半導体チップが収容されており、該パッケージ本
体Iの下面には、前記半導体チップの電杼を外部に接続
する端子として多数のピン状のり一ド2がマトリクス状
に配設されている。
FIG. 4 is a diagram showing an example of a conventional pin grid array package. This is the package body 1 of Serakutsuku etc.
A semiconductor chip is housed in the package body I, and a large number of pin-shaped glues 2 are arranged in a matrix on the lower surface of the package body I as terminals for connecting the electric shuttle of the semiconductor chip to the outside. .

〔発明が解決しようとする課題] 上記のような従来のピングリッドアレイパッケージでは
、リードの長さがすべて同じ長さであり且つ表面実装で
あるため、プリント板への実装時にはパッケージをゲー
ジ板を用いてガイドするか、又は画像処理装置で位置合
わせする必要があった。
[Problems to be Solved by the Invention] In the conventional pin grid array package as described above, all the leads are the same length and are surface mounted, so when mounting the package on a printed board, the package must be mounted on a gauge plate. It was necessary to use an image processing device to guide the image, or to perform alignment using an image processing device.

しかしゲージ板を用いる方法はパッケージ本体がセラミ
ックであると、その外形の寸法精度が悪いため、位置合
わせ精度は良くなく、また画像処理装置を用いる方法は
工数が増加するといった問題があった。
However, the method using a gauge plate has a problem in that when the package body is made of ceramic, the dimensional accuracy of the outer shape is poor, resulting in poor positioning accuracy, and the method using an image processing device increases the number of man-hours.

本発明は上記従来の問題点に鑑み、プリント板への実装
時の位置合わせが容易な半導体パッケージを提供するこ
とを目的とする。
SUMMARY OF THE INVENTION In view of the above conventional problems, it is an object of the present invention to provide a semiconductor package that is easy to align when mounted on a printed board.

〔課題を解決するための手段] 上記目的を達成するために、本発明の半導体装置ではパ
ッケージ裏面に多数のピン状リードが所定のピッチでマ
トリクス状に配設された表面実装型のピングリッドアレ
イパッケージにおいて、上記マトリクス状に配置された
りード2の四隅の少なくとも対角の二つの隅の該リード
2から所定のピッチより長い距離を隔てた位置に該リー
ド2より長さの長い位置合わせ用のピン3を設けたこと
を特徴とする。
[Means for Solving the Problems] In order to achieve the above object, the semiconductor device of the present invention uses a surface-mounted pin grid array in which a large number of pin-shaped leads are arranged in a matrix at a predetermined pitch on the back surface of the package. In the package, at least two diagonal corners of the four corners of the leads 2 arranged in a matrix are located at positions spaced apart from the leads 2 by a distance longer than a predetermined pitch. It is characterized by having a pin 3.

〔作 用〕[For production]

ピングリッドアレイパッケージにおいて、所定のピッチ
でマトリクス状に配置されたリードより長さの長いピン
を該マトリクス状に配置されたリードの四隅の少なくと
も対角の二つの隅のリードから該所定のピッチより長い
距離を隔てた位置に設けたことにより、該ピングリッド
アレイパッケージをプリント板に表面実装で搭載すると
き、プリント板に前記の長いピンに対向する位置にガイ
ド孔を表面実装のリードの接続に影響を与えることなく
設けることができ、、該孔に長いピンを挿入することに
より容易に位置決めすることができる。
In a pin grid array package, pins longer than the leads arranged in a matrix at a predetermined pitch are inserted from the leads at at least two diagonal corners of the four corners of the leads arranged in a matrix at a predetermined pitch. By providing the pin grid array package at positions separated by a long distance, when mounting the pin grid array package on a printed circuit board by surface mounting, guide holes are placed on the printed board at positions opposite to the long pins for connection of surface mount leads. It can be installed without affecting the hole, and can be easily positioned by inserting a long pin into the hole.

(実施例〕 第l図は本発明の実施例を示す図であり、(a)は正面
図、(b)はa図のZ矢視図である。
(Embodiment) FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) is a front view and (b) is a view taken along the Z arrow in FIG.

同図において、1は半導体チップを内蔵したパッケージ
本体であり、該パッケージ本体1の下面には、前記半導
体チップの電極を外部に接続する多数のピン状の例えば
直径0.15amのりード2がマトリクス状に配置して
設けられていることは第4図で説明した従来例と同様で
あり、本実施例の要点は、マトリクス状に配列されたり
ード2の四隅に該マトリクス状に配列されたり一ド2の
ビッチPと同一のピッチで該リード2より長さの長い位
置合わせ用の例えば直径0. 4 rrrra程度のピ
ン3を設けたことである。この位置合わせ用ピン3の位
置はりード2のピッチと同一ではあるが隣接したピンが
ないため一番近いリード2から7′TPの位置にある。
In the figure, reference numeral 1 denotes a package body with a built-in semiconductor chip, and on the bottom surface of the package body 1, there are many pin-shaped leads 2 having a diameter of 0.15 am, for example, to connect the electrodes of the semiconductor chip to the outside. The fact that they are arranged in a matrix is the same as the conventional example explained in FIG. For example, a diameter of 0.0 mm is used for positioning, which has the same pitch as the pitch of the lead 2 and has a longer length than the lead 2. The reason is that the pin 3 of about 4 rrrra is provided. The position of the positioning pins 3 is the same as the pitch of the leads 2, but since there are no adjacent pins, they are located 7' TP from the nearest lead 2.

このため微細ピッチ、例えばP=1.27mmのような
場合でも一番近いリード2からはPx,7’T= 1.
 8 mmと離れ、搭載するプリント板位置決め用のス
ルーホールを設けることが十分可能である。
Therefore, even in the case of a fine pitch, such as P=1.27 mm, from the nearest lead 2, Px,7'T=1.
It is quite possible to provide a through hole for positioning the printed board to be mounted at a distance of 8 mm.

この実施例では位置合わせ用ピン3は長く且つピン数が
少ないので、リード2より径を太くして強度を大きくし
てある。
In this embodiment, the alignment pins 3 are long and have a small number of pins, so they are made thicker in diameter than the leads 2 to increase their strength.

このように構威された本実施例は、第2図に示す順序で
第3図の如く実装される。即ち各リード2には予備半田
が施され、同時に搭載するプリント板4にはパッド5に
半田ペーストが印刷される。
This embodiment thus configured is implemented as shown in FIG. 3 in the order shown in FIG. That is, preliminary solder is applied to each lead 2, and at the same time, solder paste is printed on the pads 5 of the printed board 4 to be mounted.

なおこのプリント板4には予め位置決め用のスルーホー
ル6が設けられる。次にこのプリント板4の位置決め用
スルーホール6に本実施例の位置決め用ピン3を挿入し
て本実施例を載置し、次いでリフロー加熱して半田を溶
融しバッド5にリード2を半田付けする。次いでプリン
ト板4の裏面か半田ディプにより位置合わせ用スルーホ
ール6に位置合わせ用ピン3を半田付けして完或するの
である。
Note that this printed board 4 is provided with a through hole 6 for positioning in advance. Next, the positioning pin 3 of this embodiment is inserted into the positioning through hole 6 of this printed board 4, and the present embodiment is placed thereon.Then, the solder is melted by reflow heating and the lead 2 is soldered to the pad 5. do. Next, the positioning pins 3 are soldered to the positioning through-holes 6 by solder dipping on the back side of the printed board 4 to complete the process.

以上の本実施例によればプリント板への搭載時に従来の
如き特別な装置を要さず、極めて容易に位置決めができ
る。
According to the present embodiment described above, positioning can be performed extremely easily when mounting on a printed circuit board without requiring any special equipment as in the prior art.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明によれば、ピングリッドアレ
イパッケージにおいて、所定のピッチでマトリクス状に
配置されたリードの四隅の少なくとも対角の二つの隅の
リードからリードのピッチより長い距離を隔てた位置に
位置決め用のピンを設けたことにより、プリント板への
搭載時の位置合わせが容易となり、また位置ずれ不良の
発生は皆無となる。
As explained above, according to the present invention, in a pin grid array package, at least two diagonal corner leads of the four corners of the leads arranged in a matrix at a predetermined pitch are spaced apart from each other by a distance longer than the pitch of the leads. By providing positioning pins at the same positions, alignment during mounting on a printed board becomes easy, and there is no occurrence of misalignment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す図、 第2図は本発明の実施例をプリント板に搭載する手順を
示す図、 第3図はプリント板に搭載された本発明の実施例を示す
図、 第4図は従来のピングリッドアレイパッケージを示す図
である。 図において、 1はパッケージ本体、 2はリード、 3は位置合わせ用ピン、 4はフ゜リント手反、 5はパッド、 6はスルーホール を示す。
Fig. 1 shows an embodiment of the present invention; Fig. 2 shows a procedure for mounting an embodiment of the invention on a printed board; Fig. 3 shows an embodiment of the invention mounted on a printed board. FIG. 4 is a diagram showing a conventional pin grid array package. In the figure, 1 is a package body, 2 is a lead, 3 is a positioning pin, 4 is a print handle, 5 is a pad, and 6 is a through hole.

Claims (1)

【特許請求の範囲】[Claims] 1、パッケージ裏面に多数のピン状リードが所定のピッ
チでマトリクス状に配設された表面実装型のピングリッ
ドアレイパッケージにおいて、上記マトリクス状に配置
されたリード(2)の四隅の少なくとも対角の二つの隅
の該リード(2)から該所定のピッチより長い距離を隔
てた位置に該リード(2)より長さの長い位置合わせ用
のピン(3)を設けたことを特徴とする半導体パッケー
ジ。
1. In a surface mount type pin grid array package in which a large number of pin-shaped leads are arranged in a matrix at a predetermined pitch on the back of the package, at least the diagonal corners of the four corners of the leads (2) arranged in the matrix are A semiconductor package characterized in that positioning pins (3) having a longer length than the leads (2) are provided at positions separated from the leads (2) at two corners by a distance longer than the predetermined pitch. .
JP1240716A 1989-09-19 1989-09-19 Semiconductor package Pending JPH03104149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1240716A JPH03104149A (en) 1989-09-19 1989-09-19 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1240716A JPH03104149A (en) 1989-09-19 1989-09-19 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH03104149A true JPH03104149A (en) 1991-05-01

Family

ID=17063645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1240716A Pending JPH03104149A (en) 1989-09-19 1989-09-19 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH03104149A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04121753U (en) * 1991-04-19 1992-10-30 京セラ株式会社 Plug-in type semiconductor device storage package
US5490040A (en) * 1993-12-22 1996-02-06 International Business Machines Corporation Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04121753U (en) * 1991-04-19 1992-10-30 京セラ株式会社 Plug-in type semiconductor device storage package
US5490040A (en) * 1993-12-22 1996-02-06 International Business Machines Corporation Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array

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