JPH0310534U - - Google Patents

Info

Publication number
JPH0310534U
JPH0310534U JP1989069744U JP6974489U JPH0310534U JP H0310534 U JPH0310534 U JP H0310534U JP 1989069744 U JP1989069744 U JP 1989069744U JP 6974489 U JP6974489 U JP 6974489U JP H0310534 U JPH0310534 U JP H0310534U
Authority
JP
Japan
Prior art keywords
lsi chip
recess
chip
layer
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989069744U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989069744U priority Critical patent/JPH0310534U/ja
Publication of JPH0310534U publication Critical patent/JPH0310534U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の第１実施例の構成を示す回
路基板の一部の断面図、第２図は、同じくその斜
視図、第３図は、本考案の第２実施例の構成を示
す斜視図、第４図ａ，ｂは、従来のＬＳＩチツプ
の実装構造における欠点を示す回路基板を一部の
断面図である。 １０……回路基板、１１……ベース層、１２，
１３……絶縁層、１４，１５……回路導体、１６
，１７……スルーホール、１８，２３……ボンデ
イングパツド、１９……ＬＳＩチツプ、２０……
凹部、２１……段、２２……接着剤、２４……ワ
イヤ。 FIG. 1 is a cross-sectional view of a part of a circuit board showing the structure of the first embodiment of the present invention, FIG. 2 is a perspective view thereof, and FIG. 3 is the structure of the second embodiment of the present invention. The perspective views shown in FIGS. 4a and 4b are cross-sectional views of a portion of the circuit board showing the drawbacks in the conventional LSI chip mounting structure. 10... circuit board, 11... base layer, 12,
13... Insulating layer, 14, 15... Circuit conductor, 16
, 17... Through hole, 18, 23... Bonding pad, 19... LSI chip, 20...
Recessed portion, 21...step, 22...adhesive, 24...wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路導体１４，１５と絶縁層１２，１３とを積
層して構成された回路基板１０の表面に露出して
いる絶縁層１３に、ＬＳＩチツプ１９の実装位置
に対応して、該ＬＳＩチツプ１９の平面サイズよ
りも小さめの凹部２０を形成し、該凹部２０内に
適量に施与された接着剤２２によつて、ＬＳＩチ
ツプ１９を位置決め固定することを特徴とするＬ
ＳＩチツプの実装構造。 The insulating layer 13 exposed on the surface of the circuit board 10, which is composed of laminated circuit conductors 14, 15 and insulating layers 12, 13, is provided with a layer of the LSI chip 19 corresponding to the mounting position of the LSI chip 19. An LSI chip 19 is characterized in that a recess 20 smaller than the plane size is formed, and an appropriate amount of adhesive 22 is applied inside the recess 20 to position and fix the LSI chip 19.
Mounting structure of SI chip.
JP1989069744U 1989-06-16 1989-06-16 Pending JPH0310534U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989069744U JPH0310534U (en) 1989-06-16 1989-06-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989069744U JPH0310534U (en) 1989-06-16 1989-06-16

Publications (1)

Publication Number Publication Date
JPH0310534U true JPH0310534U (en) 1991-01-31

Family

ID=31605311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989069744U Pending JPH0310534U (en) 1989-06-16 1989-06-16

Country Status (1)

Country Link
JP (1) JPH0310534U (en)

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