JPS6252967U - - Google Patents

Info

Publication number
JPS6252967U
JPS6252967U JP1985144785U JP14478585U JPS6252967U JP S6252967 U JPS6252967 U JP S6252967U JP 1985144785 U JP1985144785 U JP 1985144785U JP 14478585 U JP14478585 U JP 14478585U JP S6252967 U JPS6252967 U JP S6252967U
Authority
JP
Japan
Prior art keywords
conductive
semiconductor
wiring board
printed wiring
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985144785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985144785U priority Critical patent/JPS6252967U/ja
Publication of JPS6252967U publication Critical patent/JPS6252967U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の半導体回路装置の一実施例を
示す分解斜視図、第２図はその平面図、第３図は
その要部の断面図、第４図は本考案の半導体回路
装置の他の実施例を示す斜視図である。 １は半導体スライス、２はチツプ部分、３は電
極パツド部、４は多層プリント配線基板、５は導
電パターン、６は端子部、９は導電異方性接着剤
層、１４は半導体ウエーハである。 FIG. 1 is an exploded perspective view showing an embodiment of the semiconductor circuit device of the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a sectional view of the main parts thereof, and FIG. FIG. 7 is a perspective view showing another embodiment. 1 is a semiconductor slice, 2 is a chip portion, 3 is an electrode pad portion, 4 is a multilayer printed wiring board, 5 is a conductive pattern, 6 is a terminal portion, 9 is a conductive anisotropic adhesive layer, and 14 is a semiconductor wafer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の半導体チツプ部を連続一体とした半導体
スライスが、絶縁性接着剤に導電性粒子を一様に
分散し、面内方向には絶縁され厚み方向には導通
する導電異方性接着剤層を介して、プリント配線
基板に接合されて成る半導体回路装置。 A semiconductor slice that is made up of multiple semiconductor chip parts is made by uniformly dispersing conductive particles in an insulating adhesive, creating a conductive anisotropic adhesive layer that is insulated in the in-plane direction and conductive in the thickness direction. A semiconductor circuit device that is bonded to a printed wiring board through a wire.
JP1985144785U 1985-09-21 1985-09-21 Pending JPS6252967U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985144785U JPS6252967U (en) 1985-09-21 1985-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985144785U JPS6252967U (en) 1985-09-21 1985-09-21

Publications (1)

Publication Number Publication Date
JPS6252967U true JPS6252967U (en) 1987-04-02

Family

ID=31055710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985144785U Pending JPS6252967U (en) 1985-09-21 1985-09-21

Country Status (1)

Country Link
JP (1) JPS6252967U (en)

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