JPH03109351U - - Google Patents

Info

Publication number
JPH03109351U
JPH03109351U JP1990016236U JP1623690U JPH03109351U JP H03109351 U JPH03109351 U JP H03109351U JP 1990016236 U JP1990016236 U JP 1990016236U JP 1623690 U JP1623690 U JP 1623690U JP H03109351 U JPH03109351 U JP H03109351U
Authority
JP
Japan
Prior art keywords
fitting groove
integrated circuit
circuit element
bus line
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990016236U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990016236U priority Critical patent/JPH03109351U/ja
Publication of JPH03109351U publication Critical patent/JPH03109351U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Pressure Sensors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す図、第２図は第
１図のＡ方向矢視図である。 図において、１はシリコン基板、２はウエハス
ケール集積回路素子、３は嵌合溝、４はバスライ
ン、５はシリコンバツクパネルである。 FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a view taken in the direction of arrow A in FIG. In the figure, 1 is a silicon substrate, 2 is a wafer scale integrated circuit element, 3 is a fitting groove, 4 is a bus line, and 5 is a silicon back panel.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] シリコン基板１上にウエハスケール集積回路素
子２を支持、固定する嵌合溝３を平行に凹設する
とともに、該嵌合溝３に沿つてバスライン４を薄
膜工程により形成してなるシリコンバツクパネル
。 A silicon back panel in which a fitting groove 3 for supporting and fixing a wafer scale integrated circuit element 2 is recessed in parallel on a silicon substrate 1, and a bus line 4 is formed along the fitting groove 3 by a thin film process. .
JP1990016236U 1990-02-22 1990-02-22 Pending JPH03109351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990016236U JPH03109351U (en) 1990-02-22 1990-02-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990016236U JPH03109351U (en) 1990-02-22 1990-02-22

Publications (1)

Publication Number Publication Date
JPH03109351U true JPH03109351U (en) 1991-11-11

Family

ID=31519516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990016236U Pending JPH03109351U (en) 1990-02-22 1990-02-22

Country Status (1)

Country Link
JP (1) JPH03109351U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008268651A (en) * 2007-04-23 2008-11-06 Shiga Pref Gov Identification tag

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293750A (en) * 1986-06-13 1987-12-21 Nippon Telegr & Teleph Corp <Ntt> Wiring board and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293750A (en) * 1986-06-13 1987-12-21 Nippon Telegr & Teleph Corp <Ntt> Wiring board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008268651A (en) * 2007-04-23 2008-11-06 Shiga Pref Gov Identification tag

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