JPH03113834U - - Google Patents
Info
- Publication number
- JPH03113834U JPH03113834U JP1990024244U JP2424490U JPH03113834U JP H03113834 U JPH03113834 U JP H03113834U JP 1990024244 U JP1990024244 U JP 1990024244U JP 2424490 U JP2424490 U JP 2424490U JP H03113834 U JPH03113834 U JP H03113834U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- protective film
- showing
- film layer
- irregularities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Description
第１図は本考案に係る半導体チツプの一実施例
を示す模式的断面図、第２図〜第４図は半導体チ
ツプの製造方法を説明するための模式的断面図、
第５図は半導体チツプをパツケージングした状態
を示す模式的断面図、第６図は本考案に係る半導
体チツプの別の実施例を示す模式的断面図、第７
図ａ，ｂはフオトマスクパターンの一例を示す平
面図、第８図は従来の半導体チツプのパツケージ
ングの一例を示す斜視図である。
１１……Ｓｉ基板（半導体基板）、１６……保
護膜層、１８，１９……半導体チツプ。
FIG. 1 is a schematic cross-sectional view showing one embodiment of a semiconductor chip according to the present invention, and FIGS. 2 to 4 are schematic cross-sectional views for explaining a method of manufacturing a semiconductor chip.
FIG. 5 is a schematic cross-sectional view showing a packaged semiconductor chip, FIG. 6 is a schematic cross-sectional view showing another embodiment of the semiconductor chip according to the present invention, and FIG.
Figures a and b are plan views showing an example of a photomask pattern, and Fig. 8 is a perspective view showing an example of conventional semiconductor chip packaging. 11...Si substrate (semiconductor substrate), 16...protective film layer, 18, 19... semiconductor chip.
Claims (1)
／または半導体基板裏面側に、凹凸が多数形成さ
れていることを特徴とする半導体チツプ。 A semiconductor chip characterized in that a large number of irregularities are formed on a protective film layer constituting the outermost layer of the semiconductor chip and/or on the back side of a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990024244U JPH03113834U (en) | 1990-03-09 | 1990-03-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990024244U JPH03113834U (en) | 1990-03-09 | 1990-03-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03113834U true JPH03113834U (en) | 1991-11-21 |
Family
ID=31527213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990024244U Pending JPH03113834U (en) | 1990-03-09 | 1990-03-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03113834U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101970910B1 (en) * | 2018-01-11 | 2019-04-19 | 최성희 | Horizontal revolution type treadmill |
-
1990
- 1990-03-09 JP JP1990024244U patent/JPH03113834U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101970910B1 (en) * | 2018-01-11 | 2019-04-19 | 최성희 | Horizontal revolution type treadmill |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0279044U (en) | ||
| JPH0371630U (en) | ||
| JPH02133308U (en) | ||
| JPH0284303U (en) | ||
| JPH0268474U (en) | ||
| JPS63137942U (en) | ||
| JPH01132770U (en) | ||
| JPS6151392U (en) | ||
| JPH0384752U (en) | ||
| JPH0270444U (en) | ||
| JPH0367098U (en) | ||
| JPS62151747U (en) | ||
| JPS6376552U (en) | ||
| JPS6418733U (en) | ||
| JPS5929261U (en) | Transfer sheet for curved surface painting | |
| JPH0231154U (en) | ||
| JPH0270429U (en) | ||
| JPH01116439U (en) | ||
| JPH0247337U (en) | ||
| JPS6228757U (en) | ||
| JPS6364061U (en) | ||
| JPS6447041U (en) | ||
| JPH0395628U (en) | ||
| JPH02742U (en) | ||
| JPH03116052U (en) |