JPH03116232A - Instruction decoding device - Google Patents

Abstract

PURPOSE:To apply a group repeating function as long as the same arithmetic process is applied to data by decoding the corresponding instruction based on the instruction information and in response to the depth of a pipeline and controlling a prescribed request of an arithmetic part. CONSTITUTION:An instruction decoding part 1 includes the instruction decoding circuits 10 - 16 which decode the instructions in response to the depth of the pipeline of an arithmetic part 3 and a program delay circuit 20 which functions to make each instruction decoding circuit decode the instruction in each pre scribed timing. Then each of circuits 10 - 16 receives the instruction information and decodes a prescribed instruction in charge of the control to control the element of the corresponding arithmetic part. Thus, the influence of a pipeline process is deleted at the arithmetic part. Then a group repeating function can be applied as long as the same process is applied to data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction decoding device, and particularly to an instruction decoding device that is advantageously applied to, for example, a digital signal processor (DSP).

(Prior Art) In recent years, various digital signal processors used for speech synthesis, filters, etc. have been proposed. For example, AT&T edition, [■E 1) SP168 Di italS
Such a conventional technique is described in the information manual of ignal ProcessorJ.

A digital signal processor includes an instruction decoding circuit, which is an instruction decoding device, as well as an arithmetic unit, a storage unit, and the like, and operates according to a written program to execute predetermined processing. That is, the written program is decoded by the instruction decoding circuit as a control signal for the arithmetic unit, and the control signal is sent to the arithmetic unit to process data.

Note that the written program is held in a program storage section inside or outside the digital signal processing processor. For this reason, it is desirable to make the program as small as possible so that a program storage unit with a small capacity can be used. For example, if α, β, and γ are one group of instructions, a digital signal processing processor program repeatedly executes a small group of instructions called a group, such as α, β, γ, a, β, and γ9.8. There are many things.

Taking advantage of this property of digital signal processing processor programs, it is possible to repeatedly execute groups [
By combining instructions into group instructions H9+l],
There are known methods to reduce the size of a program. As detailed in the above-mentioned literature, this method includes, for example, providing a counter in the sequencer section, and when a numerical value N-1 is input to this counter by a command, the group existing in the cache memory is repeatedly executed N times. This is a method of program control.

Further, in digital signal processing processors, pipeline processing is used in which multiple processes are overlapped in order to increase the processing speed of the processing section.

(Problem to be Solved by the Invention) However, in such a conventional instruction decoding device, due to the pipeline processing performed in the processing section,
Since the program was decoded all at once, there was a drawback that the group repeat function could not be used even though each piece of data was subjected to the same processing. In other words, even though the same processing is performed on each piece of data, it has to be written in the storage unit as a different program.

The present invention eliminates the drawbacks of the prior art, eliminates the influence of pipeline processing in the arithmetic unit, and provides an instruction decoder that can use the group repeat function if the same processing is performed on data. The purpose is to

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an instruction decoding device that receives instruction information, decodes the instruction information, and controls an arithmetic section. It has a plurality of instruction decoding means according to the depth of processing, and each instruction decoding means decodes the corresponding instruction from the instruction information according to the depth of the pipeline that is in charge of control, and decodes the corresponding instruction from the predetermined element of the arithmetic unit. control.

(Function) According to the present invention, each command decoding means, upon receiving command information, decodes a predetermined command in charge of control, thereby controlling the elements of the corresponding arithmetic section.

(Embodiment) Next, an embodiment of the instruction decoding device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, there is shown a functional block diagram of an embodiment in which an instruction decoding device according to the present invention is applied to a digital signal processing processor. Note that this figure shows the instruction decoding section 1 and the arithmetic section 3 that are directly related to this embodiment, and the components of the digital signal processing processor that are not directly related to this embodiment are omitted.

The arithmetic unit 3 is a processing unit that executes arithmetic processing according to the control signal from the instruction decoding unit 1, and is a processing unit that executes arithmetic processing according to the control signal from the instruction decoding unit 1.
ROM150, random access memory fRAM)5
4, register (x) 60. (Yl 62. fPl
66, 1a0172, multiplier 64, multiplexer (
MUXl 68 and arithmetic logic unit (ALIJI
It has 70.

The read-only memory 50 and the random access memory 54 are storage units in which numerical data such as variables used in arithmetic processing is stored for each address. An address pointer 52 is connected to the memory 50,
The data at the address indicated by this pointer 52 can be read. That is, when read control is performed on the memory 50, data pointed to by the pointer 52 is sent to the ROM data bus 100 via the output 200.

An address pointer 56 is also connected to the memory 54,
Data at the address indicated by this pointer 56 can be read and written. That is, the memory 54 sends data at the address indicated by the pointer 56 to the RAM data bus 102 via the input/output line 204, or sends data received from the data bus 102 to the address indicated by the pointer 56, under control from the instruction decoder l. or store it in

ROM data bus 100 is an information transmission path for data stored in memory 50 and is connected to register X via output 202. The RA&l data bus 102 is
It is an information transmission path of the memory 54 and is connected to the register X via the output 208 and to the register Y via the output 206.

Registers X and Y are high-speed memories that temporarily store data sent via the data bus. register x
is connected to multiplier 64 via output 210, and register Y is connected to multiplier 64 and multiplexer 68 via output 212.

Multiplier 64 multiplies the data stored in registers X and Y, and outputs the result to register P via output 216.
It is a calculation unit that outputs to The register P is a register that stores the multiplication result calculated by the multiplier 64, and the output 21
6 to a multiplexer 68. Multiplexer 68 is a selection circuit that sends either input 212 from register Y or input 216 from register P to arithmetic logic unit 70 via output 218. Selection of the multiplexer 68 is performed according to a control signal from the arithmetic unit, which will be described later.

The arithmetic logic unit 70 is a circuit that performs arithmetic operations, etc., and sends the results of the operations to eight registers via an output 220. Register aO is a register that stores the calculation results of unit 70, and is connected to RAM data bus 102 and to unit 70 via output 222.

In addition, although the calculation section 3 in the same figure shows the H4 structure in a general digital processing processor, the 1flT1 section to which the present invention is applied is not particularly limited to this. However, for example, each component of the arithmetic unit manually inputs the tarok signal from the master clock. By inputting this clock signal, even in pipeline processing, for example, registers X and Y multiply the information sent from the data bus.
It does not overwrite information from the data bus before sending it to the data bus.

The instruction decoding section 1 is a processing section that inputs a program sent from an instruction register (not shown) from the program input terminal 200, and controls the arithmetic section 3 by pipeline processing by decoding the program. As shown in the figure, the instruction decoding section l according to this embodiment includes a plurality of instruction decoding circuits l.
It is constituted by three delay circuits 20 that output manually-generated information after a predetermined time delay. Note that the number of instruction decoding circuits and delay circuits 20 is determined by the depth of the pipeline of the calculation unit 3, and the number is not particularly limited as in this embodiment. l is formed by hardware in this embodiment.

The instruction decoding circuit IO is an instruction decoding circuit at the 0th stage of the pipeline connected to the program input terminal 300 via the program signal path 310. The instruction decoding circuit IO controls the output of the read-only memory 50, the input/output control of the random access memory 54, the control of the address pointers 52 and 56, the data bus control B of the read-only memory 50, and the data bus system (B) of the random access memory 54. The instruction decoding circuit IO performs instruction decoding for (-YIII@) and controlling these elements.

The instruction decoding circuit 12 is an instruction decoding circuit in the first stage of the pipeline connected to the program input terminal 300 via the delay circuit 20-2. The instruction decoding circuit 12 decodes the instruction for controlling the multiplier output register P, and outputs the jump symbol 2.
This is controlled via the control signal path shown by the dotted line.

The instruction decoding circuit 14 includes delay circuits 20-1 and 20-2.
This is an instruction decoding circuit in the second stage of the pipeline, which is connected to the program input terminal 3oo via the program input terminal 3oo. Instruction decoding circuit 14 decodes instructions for controlling multiplexer 68, arithmetic logic unit 70, and register aO. The command decoding circuit 14 decodes the commands of these elements and controls them via a control signal path indicated by a dotted line with an interlace symbol 3.

The instruction decoding circuit 16 is a third stage instruction decoding circuit in the pipeline connected to the program input terminal 300 via delay circuits 20-1, 20-2 and 20-3. The instruction decoding circuit 16 includes a register aO, a data bus 102 . Random access memory 54. An instruction decoding circuit 16, which decodes instructions for controlling the address pointer 56, is connected to these via a control signal path indicated by a dotted line with an interlace symbol 4, and performs the control thereof.

Next, the operation of this embodiment will be explained using a specific example.

D=Σ A, XBI --- (11l11 Regarding the case of performing the calculation shown in equation (1).

The operations of the instruction decoder l and the arithmetic unit 3 at each time will be specifically explained. However, it is assumed that data A and B in formula 1 111 are expanded in the read-only memory 50 and the random access memory 54 in a lined manner.

In this operation example, the following command (1) is first input to the program input terminal 300, then command (2) is input five times, and finally command (3) is input manually.

Contents of instruction (1): Input data A and B from read-only memory 50 and random access memory 54 to registers X and Y.

The address pointer 52 of the read-only memory 50 and the address pointer 56 of the random access memory 54 are updated by 1.

The product of the data stored in registers X and Y is calculated and input to register P.

The contents of register P are input to register aO through arithmetic logic unit 70.

Contents of instruction (2): Input data A and B from read-only memory 50 and random access memory 54 to registers X and Y.

The address pointer 52 of the read-only memory 50 and the address pointer 56 of the random access memory 54 are updated by 1.

The product of the contents of registers X and Y is calculated and the result is input to register P.

The sum of the Fi values stored in register aO and register P is calculated using arithmetic logic unit 70 and stored in register aO.

Contents of instruction (3): Input the contents of register aO to random access memory 54.

The operation of the arithmetic unit 3 and the instruction decoder I is shown.

(Time 1): The instruction decoding circuit IO inputs the data A and B of instruction (1) from the read-only memory 50 and the random access memory 54 to the registers X and Y. The address pointer 52 of the read-only memory 50 and the random access The address pointer 56 of the memory 54 is updated by 1.'' is decoded.

As a result, Wt(mAr, B) are transferred from the read-only memory 5a and the random access memory 52 and stored in registers X and Y, respectively.

Also, the address pointers 52 and 56 are incremented by 1. (Time 2): The instruction decoding circuit IO inputs [data A and B of instruction (2)] from the read-only memory 50 and the random access memory 54 to the registers X and Y. do. The address pointer 52 of the read-only memory 50 and the address pointer 56 of the random access memory 54 are updated by 1. Decipher part 1.

The instruction decoding circuit I2 reads the instruction (11 [registers X, Y
The part of 6J which calculates the product of the contents and inputs it to register P is decoded.

AI X Bl is calculated by the instruction decoding circuit 12 in the multiplier 64, and the result is stored in the register P.

Also, the read-only memory 50 is read-only by the instruction decoding circuit IO.
．． Numerical values A2 and B2 are transferred from random access memory 54 and stored in registers xi3 and Y, respectively.

Furthermore, the pointers of address pointers 52 and 56 are updated by 1.

(Time 3): The instruction decoding circuit 10 inputs the data A and B of the instruction (2) from the read-only memory 50 and the random access memory 54 to the registers X and Y. The address pointer 52 of the read-only memory 50 and the random access The address pointer 56 of the memory 54 is updated by 1.'' is decoded.

The instruction decoding circuit 12 reads “registers X, Y” of instruction (2).
Calculate the product of the contents of and input it to register P. ” part.

The instruction decoding circuit 14 decodes the part of the instruction (1) that says, "Input the contents of register P to register aO through arithmetic logic unit 70."

The contents of register P (A1×8,
) is stored in register aO through arithmetic logic unit 70.

Further, the instruction decoding circuit 12 outputs AzxBa to the multiplier 64.
The result is stored in register P.

Furthermore, read-only memory 5 is read-only by instruction decoding circuit IO.
0, Random access memo, data A3, B from Su54
3 are transferred and stored in registers X and Y, respectively.

Further, the address pointers 52 and 56 are updated by 1 by the instruction decoding circuit IO.

(Time 4): The instruction decoding circuit IO executes the instruction (2) "Input data A and B from the read-only memory 50 and random access memory 54 to registers X and Y. Update address pointers 52 and 56 by 1." decipher the part.

The instruction decoding circuit 12 reads “registers X, Y” of instruction (2).
decipher the part "Calculate the product of the contents of and input it to register P."

The instruction decoding circuit 14 reads “register aO1” of instruction (2).
The sum of the contents of P is computed using arithmetic logic unit 70 and entered into register aO. ” part.

The instruction decoding circuit 14 calculates the contents (atxoz) of the child register P of the register aO in the arithmetic logic unit 70, and stores this in the register aO.

Further, the instruction decoding circuit 12 calculates A3XB2 using a multiplier, and the result is stored in the register P.

Further, the read-only memory 5
0, data A4, B4 from random access memory 54
are transferred and stored in registers X and Y, respectively.

Further, the address pointer 52 .
56 is updated by 1.

(Time 5): The instruction decoding circuit IO executes the instruction (2) "Input data A and B from the read-only memory 50 and random access memory 54 to registers X and Y. Update address pointers 52 and 56 by 1." decipher the part.

The instruction decoding circuit 12 reads [registers X, Y
decipher the part "Calculate the product of the contents of and input it to register P."

The instruction decoding circuit 14 reads [register aO1 of instruction (2)]
The sum of the contents of P is computed using arithmetic logic unit 70 and entered into register aO. ” part.

The instruction decoding circuit 14 calculates the contents of the register aO+the contents of the register P (A, XB3) in the arithmetic logic unit 70, and stores the result in the register aO.

Further, data A4XB4 is calculated by the multiplier 64 by the instruction decoding circuit 12, and the result is stored in the register P.

Further, the read-only memory 5
0, data As, B from random access memory 54
s is transferred and stored in registers X and Y, respectively.

Further, the address pointers 52 and 56 are updated by 1 by the instruction decoding circuit IO.

(Time 6): The instruction decoding circuit 10 inputs the data A and B of the instruction (2) from the read-only memory 50 and the random access memory 54 to the registers X and Y. The address pointers 52 and 56 are updated by 1.J decipher the part.

The instruction decoding circuit 12 reads [registers X, Y
The product of the contents of is calculated and the part of J input into register P is decoded.

The instruction decoding circuit 14 reads “register aO5” of instruction (2).
The sum of the contents of P is computed using arithmetic logic unit 70 and entered into register aO. ] Decipher the part.

The instruction decoding circuit 14 calculates the contents of the register aO+the contents of the register P (A4XB4) in the arithmetic logic unit 7o, and this is stored in the register aO.

Further, the instruction decoding circuit 12 outputs AsXBs to the multiplier 64.
The result is stored in register P.

Furthermore, read-only memory 5 is read-only by instruction decoding circuit IO.
0, data A6, B6 from random access memory 54
are transferred and stored in registers X and Y, respectively.

Further, the address pointer 52 .
56 is added by 1.

(Time 7): The instruction decoding circuit 12 decodes the part of instruction (2) that says "calculate the product of the contents of registers X and Y and manually input it to register P."

The instruction decoding circuit 14 reads “register aO,
The sum of the contents of P is calculated using arithmetic logic unit 7o and entered into register aO. ” part.

The instruction decoding circuit 14 calculates the contents of the register aO+the contents of the register P (A5XB5) in the arithmetic logic unit 7o, and this is stored in the register aO.

Further, the instruction decoding circuit 12 outputs AaxBa to the multiplier 64.
The result is stored in register P.

(Time 8): The instruction decoding circuit 14 calculates the sum of the contents of the register aO1P of the instruction (2) using the arithmetic logic unit 70, and decodes the part 6J input to the register aO.

The instruction decoding circuit 14 calculates the contents of the register aO+the contents of the register P (A6X os) in the arithmetic logic unit 70, and stores this in the register an.

(Time 9): The instruction decoding circuit 16 inputs the contents of the register aO of the instruction (3) into the random access memory 54. The part J is decoded.

The instruction decoding circuit 16 uses the contents of register aO (formula (1)
The solution rDJ) is stored in the random access memory 54.

As described above, according to the present embodiment, the instruction decoding unit 1 includes instruction decoding circuits 10 to 16 that decode instructions according to the depth of the pipeline of the corresponding arithmetic unit 3, and each instruction decoding circuit 10 to 16 having a predetermined A program delay circuit 20 is provided so that the program is executed at the correct timing. A plurality of instruction delay circuits 20 and instruction decoding circuits 10 to 1 divided according to the number of pipeline stages
6, the operation of the calculation unit 3 is different except that time 4, time 5, and time 6 are equal, but the operation from 1 hour 1 to 9 is based on the 5 times of instruction (1) and instruction (2). It is realized by three types of repetition and instruction 3.

Therefore, the program control unit B (not shown) can use a group repeat function, and in this example, it is possible to use four instructions including an instruction specifying the number of repeats. As described above, according to this embodiment, if the arithmetic processing on the data is the same, the repeat function can be used and the program size can be reduced.

Although the present invention is applied to a digital processor in this embodiment, the present invention is not particularly limited to this, and the present invention can of course be applied to any information processing apparatus that performs pipeline processing.

(Effects of the Invention) As described above, the instruction decoding device according to the present invention can use the group repetition function without being affected by pipeline processing if the contents of the 7vi arithmetic processing on data are the same. The instruction decoding device according to the present invention includes:
This is especially true when a program is formed by a collection of several different calculation processes, and the contents of each calculation process can be divided into common data group types, and the types of these groups are approximately equal to the number of pipeline stages in the calculation section. It is valid.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram when the instruction decoding device according to the present invention is applied to a digital processor. l. 3. 10-16゜20. 50, . 52.56 54. 60°62, . 64, . 66, . 68, . 70°72. Main part - eye explanation instruction decoding part 0. Arithmetic unit 3. Instruction decoding circuit, delay circuit 3. Read-only memory address pointer 0. Random access memory register X8. Register Y 19 Multiplier Register P 1. Multiplexer 1. Arithmetic logic unit 0. register a0

Claims (1)

[Scope of Claims] 1. An instruction decoding device that receives instruction information, decodes the instruction information, and controls an arithmetic unit, wherein the device decodes a plurality of instructions according to the depth of pipeline processing of the arithmetic unit. Each of the instruction decoding means decodes a corresponding instruction from the instruction information according to the depth of the pipeline to be controlled, and controls a predetermined element of the arithmetic unit. Instruction decoding device. 2. The apparatus according to claim 1, wherein the instruction information is sent from an instruction storage section, and between the instruction storage section and the instruction decoding means,
An instruction decoding device comprising an instruction delaying means for delaying the sending of the instruction information according to the depth of the pipeline of the arithmetic unit controlled by the instruction decoding means.