JPH0311691B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counting circuit for creating any of the various gate signals required in a synchronous digital circuit.

Conventionally, in this type of circuit, creating gate signals with different gate widths has been achieved by providing separate counting circuits with different counting speeds and appropriately combining their output signals. However, this method has the disadvantage that the counting circuits are duplicated, resulting in a somewhat complicated and uneconomical configuration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a counting circuit having a plurality of counting speeds and having a simpler configuration than the conventional counting circuit for obtaining arbitrary repetitive gate signals having different gate widths.

In order to achieve the above object, the counting circuit according to the present invention includes first, second and third counting means which are continuously connected, and when the output of the first counting means is within a first predetermined range, the counting circuit according to the present invention The output of the counting means 1 is
means for making the output of the third counting means an enable signal for each of the second counting means when the output of the third counting means is within a second predetermined range, the second counting means By decoding the output signals of , repetitive gate signals having mutually different gate widths are obtained.

According to the above structure, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a counting circuit according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit shown in FIG. In Figure 1,
1 is a clock signal input terminal, 2 is a ripple carry output terminal of the counter 9, 3 is a first stage output terminal of the counter 10, 4 is a next stage output terminal of the counter 10, 5 is a ripple carry output terminal of the counter 10, and 6 is a ripple carry output terminal of the counter 10. An output terminal of the counter 11, 7 an enable input terminal of the counter 10, 8 an enable input terminal of the counter 11, 9 a free-running quaternary counter, 10 a quaternary counter whose counting is controlled, 11 is a binary counter whose counting is controlled, and 12 is an OR gate for synthesizing the ripple carry output signal of the counter 9 and the output signal of the counter 11.

In FIG. 2, numerals 1 to 6 indicate voltage waveforms of signals appearing or applied to each terminal of 1 to 6 in FIG. 1, respectively. This is an example of a gate signal created by decoding the output signals 3 and 4 of the counter 10 of No. 13.

In addition, in this embodiment, within the first predetermined range of the first counting means described in the claims refers to the self-propelled type 4.
The high level period of the output of the base counter 9 and the period within the second predetermined range of the third counting means mean the high level period of the output of the quaternary counter 10, respectively.

In the circuit of FIG. 1, when power is applied so that the circuit functions normally and a clock signal as shown by 1 in FIG. 2 is supplied to terminal 1, first the counter 9
starts operating and counts 4 clocks,
A ripple carry signal of one clock width as shown by 2 in FIG. 2 is output to terminal 2. This ripple carry signal is supplied to the enable input terminal 7 of the counter 10 through the OR gate 12. Since the counter 10 operates to count clocks only while a signal is supplied to the enable input terminal 7, the counter 10 operates while a ripple carry signal of one clock width is supplied to the enable input terminal 7.
0 counts only one clock. That is, in this case, the counter 10 can also be seen as counting the number of ripple carry signals output from the first stage counter 9. Therefore, when the counter 10 counts four ripple carry signals from the counter 9,
A ripple carry signal of one clock width as shown at 5 in FIG. 2 is output to the terminal 5. This ripple carry signal is supplied to the enable input terminal 8 of the counter 11 at the next stage. Counter 11 is counter 10
Similarly, since the clock is counted only while the signal is being supplied to the enable input terminal 8, it can be seen as counting the number of ripple carry signals of the counter 10.

Here, in this circuit, the output signal of the counter 11 is supplied to the enable input terminal 7 of the counter 10 through the OR gate 12. In this way, the counter 10 counts the clock while the signal is supplied to the enable input terminal 7, that is, while the signal is output to the output terminal 6 of the counter 11, so the ripple carry signal of the counter 9 is The clock continues to be counted regardless, and eventually a ripple carry signal is outputted to the terminal 5 again. When the ripple carry signal is output again to the terminal 5, the counter 11 counts one clock again, and the output signal is no longer output as shown at 6 in FIG. As a result, the enable input signal for the counter 10 disappears, so the counting operation of the counter 10 is stopped and the state returns to the initial state. As is clear from the voltage waveform in Figure 2, the above operation is performed by the counter 10.
If there is no feedback signal from the output of counter 11 at the enable input terminal of , if there is a feedback signal from the output of the counter 11, the counting speed of the counter 10 will be at the speed of the clock supplied to the counter 10.

As is clear from the above explanation, the counting circuit according to the present invention continuously connects three counting sections to perform counting sequentially, and feeds back the output of the final stage counter to the middle stage counter. By configuring the counter to also count the clocks counted by the first stage, it can be operated as a counting circuit with a plurality of counting speeds. Therefore, it is possible to obtain arbitrary repetitive gate signals with different gate widths using one counting circuit with this simple configuration.

As a modification of the present invention, a configuration may be considered in which the number of stages of the counter, the output terminal of the feedback circuit, or the clock signal supplied to each counter is changed appropriately.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a counting circuit according to the present invention, and FIG. 2 is a voltage waveform diagram of various parts and usage examples for explaining the operation of FIG. 1. 1...Clock signal input terminal, 2...Counter 9
ripple carry output terminal, 3...Counter 10
4... Output terminal of the next stage of the counter 10, 5... Ripple carry output terminal of the counter 10, 6... Output terminal of the counter 11, 7... Enable signal input of the counter 10 Terminal, 8... Enable signal input terminal for counter 11, 9... Free-running quaternary counter, 10... Quaternary counter with controlled counting, 11... Binary counter with controlled counting. , 12
...Logic gate.

Claims (1)

[Claims] 1 continuously connected first, second and third counting means, and when the output of the first counting means is within a first predetermined range, the output of the first counting means;
means for making the output of the third counting means an enable signal for each of the second counting means when the output of the third counting means is within a second predetermined range, the second counting means 1. A counting circuit characterized in that the counting circuit is configured to obtain repetitive gate signals having mutually different gate widths by decoding the output signal of the counting circuit.