JPH0444415A - Pulse generation circuit - Google Patents

Abstract

PURPOSE:To remarkably decrease the number of wires and the number of elements by applying the output or its inverse of two flip-flop circuits or above selected optionally to each input of a multi-input NAND circuit and using the output of the multi-input NAND circuit to the entire output of the pulse generating circuit. CONSTITUTION:Flip-flop circuits 11 and 12 are connected in series, the data inversion output terminal of the flip-flop circuit 12 and the input terminal of the flip-flop circuit 11 are connected to form the frequency divider circuit of loop configuration. Then the data inversion output terminal of the flip-flop circuit 11 and the output terminal of the flip-flop circuit 12 are connected to the input terminal of a NAND circuit 13, from the output terminal where a desired pulse is obtained. Thus, the pulse generating circuit is realized where one negative pulse is generated from four clock signal inputs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generation circuit in which a plurality of 7-foot registers are connected in a ring.

[Conventional technology]

Conventionally, a ring counter has been used as a pulse generating circuit. A ring counter is a ring counter in which shift registers are connected in a ring, and by setting one 1 as an initial value, it counts the shift clock according to the bit position where 1 exists. This counter is used as a pulse generating circuit because it can have any period and can create any waveform by combining the calculation outputs from the gates.

FIGS. 9 and 10 (
The explanation will be based on a) to (f).

Figure 9 shows three flip-flop circuits 31, 32, 33.
FIG. 10 is an electric circuit diagram of a pulse generating circuit composed of a NOR circuit 34 and a NOR circuit 34, and a time chart showing the operation of each part of the circuit. In these drawings, CLK represents a clock input terminal, D represents a data input terminal, Q represents a data output terminal, and QB represents an inverted data output terminal.

In the pulse generation circuit shown in FIG. 9, FIGS.
As can be seen from f), when the clock input signal input to CLK is 11, the data output X1 of the flip-flop circuit 31 and the data output X2 of the flip-flop circuit 32 each indicate rLJ, and the data output X2 of the flip-flop circuit 33 indicates rLJ. Data output X3 changes from rHJ to "L".

Therefore, the NOR circuit 34 after time t1 is x
Sx, x are all rLJ and X4 is rHJl
Hold 2 3. Next, at time t2, Xl changes to rHJ.

This is because X4 was at rHJ at time t, and its output was given to the flip-flop circuit 31. Furthermore, rLJ is maintained for all X 1X3. The output X4 of the NOR circuit 34 after time t2 is:
Since Xl is rHJ, it changes to rL and J. Next, at time t3, Xl or "L", X2 changes to rHJ, and X
3 holds "L". NOR circuit 3 after time t3
The output X of 4 holds rLJ since X2 is rHJ.

At time t4, the flip-flop circuit 3 is similarly shifted.
3 data output X3 becomes rHJ. X at 15
1X2 and X3 all become rLj, and the output X4 of the NOR circuit 34 changes to rHJ after time 15 has elapsed. The state of each flip-flop at this point is t
The state is the same as at one point in time, and the same operation is repeated thereafter. Therefore, the output OUT of the pulse generation circuit obtained from the inverted data output terminal of the flip-flop circuit 31 is
A negative pulse is generated once every four clock signals.

[Problem to be solved by the invention]

In order to generate a pulse once every N times of the clock signal using such a pulse generation circuit, it is necessary to use an NO.
An R circuit is required. For example, in a pulse generation circuit that generates a pulse once every eight clock signals,
NOR with 7 flip-flop circuits and 7 input terminals
Furthermore, a pulse generating circuit that generates a pulse once every 16 clock signals requires 15 flip-flop circuits and a NOR circuit having 15 input terminals.

In this way, in order to generate a pulse with a long period (large value of N) using a conventional circuit, many flip-flop circuits and multi-input NOR circuits are required, and the number of wirings on the circuit increases. There is a problem. In particular, the above-mentioned 1
A NOR circuit having five input terminals is too complicated to be practical.

The present invention solves these problems.

[Means to solve the problem]

The outputs or inverted outputs of two or more arbitrarily selected flip-flop circuits are respectively input to a multi-input NAND circuit, and the output of this large-power NAND circuit is used as the output of the entire pulse generation circuit.

[Effect]

According to the pulse generation circuit according to the present invention, a pulse signal having a desired period is generated by combining two or more signals having the same waveform with different timings. The number of flip-flop circuits required to configure this pulse generation circuit is
When the desired pulse period is N times the clock signal, (N/
2) It is a piece.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

Figure 1 shows two flip-flop circuits 11, 12 and NA
The electric circuit diagram of the pulse generating circuit of this embodiment, which is composed of the ND circuit 13, and FIGS. 2(a) to 2(f) are time charts showing the operation of each part of the circuit. In these drawings, CLK is a clock input terminal, OUT is an output terminal of a pulse generation circuit, D is a data input terminal, Q is a data output terminal, and QB is an inverted data output terminal.

In the pulse generation circuit shown in FIG. 1, a flip-flop circuit 11 and a flip-flop circuit 12 are connected in series, and the inverted data output terminal of the flip-flop circuit 12 is connected to the input terminal of the flip-flop circuit 11.
A loop-shaped frequency dividing circuit is configured. The inverted data output terminal of the flip-flop circuit 11 is connected to either the output terminal of the flip-flop circuit 12 or the input terminal of the NAND circuit 13, and a desired pulse is obtained from the output terminal of the NAND circuit 13.

Next, the operation of the pulse generating circuit shown in FIG. 1 will be explained using FIGS. 2(a) to 2(f).

First, when the clock input signal input to CLK is at time 11, the data output X1 of the flip-flop circuit 11
is "L", and the inverted data output X2 indicates rHJ. Moreover, the data output X3 of the flip-flop circuit 12 is “
"L", the inverted data output X4 changes to rHJ. t1
Since the inputs X SX to the NAND circuit 13 at this time are rHJ and rLJ, respectively, the output of the NAND circuit 13 after the lapse of time t1 changes to rHJ. This output becomes the output of the pulse generation circuit.

At the next time t2, data rHJ of X4 at time t1 is applied to the input of the flip-flop circuit 11, so the data output X1 changes to "H" and the inverted data output X2 changes to rLJ. Since the data rLJ of Xl at time t1 is applied to the input of the flip-flop circuit 12, the data output X3 holds "L" and the inverted data output X4 holds rHJ. Inputs X2 and X3 to the NAND circuit 13 at time t2
Since both are rLJ, the output of the NAND circuit 13 after time t2 holds rHJ, and this output becomes the output of the pulse generation circuit.

At the next 13 time points, the data rHJ of X4 at time t2 is applied to the input of the flip-flop circuit 11, so the data output X1 holds "H" and the inverted data output X2 holds rLJ. Since the data rHJ of Xl at time t2 is applied to the input of the flip-flop circuit 12, the data output X3 changes to "H" and the inverted data output X4 changes to rLJ. Inputs X2 and X to the NAND circuit 13 at time 13
are rLJ and rHJ, respectively, so N after time t3 has passed.
The output of the AND circuit 13 holds rHJ, and this output becomes the output of the pulse generation circuit.

At the next time t4, data rLJ of X4 at time t° is applied to the input of the flip-flop circuit 11, so the data output X1 changes to "L" and the inverted data output X2 changes to "H".Flip-flop circuit Since the data rHJ of Xl at time 13 is given to the input of 12, the data output X3 holds "H" and the inverted data output X4 holds rLJ. Inputs X2 and X3 to the NAND circuit 13 at time t4
Since both are rHJ, the output of the NAND circuit 13 after time t4 changes to rLJ, and this output becomes the output of the pulse generation circuit.

Since the data outputs X1 to X4 at the next time t5 become the same outputs as at time t1, the output of the pulse generation circuit also changes to rHJ, which is the same as at time t1.

In this way, after t5, the same data output as after t1 is repeated, so the output of the pulse generation circuit generates one negative pulse for every four clock signals.

This embodiment uses 2' flip-flops and one NAN
By using the D circuit, it was possible to manufacture a pulse generating circuit that generates one negative pulse for every four clock signals.

Generally, a pulse generation circuit having a period N times that of a clock signal may be manufactured using (N/2) flip-flop circuits.

Since the pulse generating circuit of the conventional example described above was composed of three flip-flops and one NOR circuit, it can be seen that the number of wiring lines and the number of elements can be significantly reduced by this embodiment.

Next, another embodiment of the present invention is shown in FIG.

Figure 3 shows three flip-flop circuits 21.22.23
FIGS. 4(a) to 4(g) are electrical circuit diagrams of the pulse generating circuit of this embodiment, which is composed of the NAND circuit 24 and the NAND circuit 24, and are time charts showing the operation of each part of the circuit. In addition, in these drawings, as in FIG. 1, CLK is a clock input terminal, OUT is an output terminal of the pulse generation circuit, D is a data input terminal, Q is a data output terminal, and QB is an inverted data output terminal. There is.

The pulse generation circuit shown in FIG. 3 has flip-flop circuits 21 to 23 connected in series, and the inverted data output terminal of the flip-flop circuit 23 and the input terminal of the flip-flop circuit 21 are connected to form a loop. A frequency dividing circuit is constructed. And the flip-flop circuit 22
The inverted data output terminal of the NAND circuit 23 and the output terminal of the flip-flop circuit 23 are connected to the input terminal of the NAND circuit 13.
A desired normal is generated from the output terminal of the AND circuit 13.

Next, the operation of the pulse generating circuit shown in FIG. 3 will be explained using FIGS. 4(a) to 4(g).

First, when the clock input signal input to CLK is at time 11, the data output X1 of the flip-flop circuit 21
indicates rLJ. Also, the flip-flop circuit 22
The data output X2 is rLJ, and the inverted data output X3 is r
It shows HJ. Furthermore, the data output X4 of the flip-flop circuit 23 is "L", and the inverted data output X5 is rH.
Changes to J. Since the human power X3 and X4 to the NAND circuit 24 at time t1 are rHJ and rLJ, respectively, the output of the NAND circuit 13 after time t1 is rHJ. This output becomes the output of the pulse generation circuit.

At the next time t2, data rHJ of X5 at time t is applied to the input of the flip-flop circuit 21, so the data specific power X1 changes to rHJ.

In addition, the input of the flip-flop circuit 22 is
Since the data "L" of 1 is given, the data output X2 is "L" and the inverted data output X3 holds rHJ. Furthermore, the input of the flip-flop circuit 23 is X at time t.
Since the data "L" of 2 is given, the data output X4 is "L" and the inverted data output X is held rHJ. The input X SX to the NAND circuit 24 below at time t2 is r
HJ, rLJ, NAND circuit 1 after time t2
The output of No. 3 holds rHJ, and this output becomes the output of the pulse generation circuit.

From the next time t to time t, the data output moves in the same way as at time tt2, and the output of the pulse generation circuit is
Hold "H".

At the next 16 time points, the data rLJ of X5 at time t is applied to the input of the flip-flop circuit 21, so the data output X1 holds rLJ.

Also, the input of the flip-flop circuit 22 is X at the time t5.
Since the data rLJ of l is given, the data output X changes to "L" and the inverted data output X3 changes to rHJ. Furthermore, the input of the flip-flop circuit 23 is X at time t.
Since the data rHJ of 2 is given, the data output X4 holds "H" and the inverted data output X holds rLJ. t
Since the input X 1X to the NAND circuit 24 at the 6th time point is all rHJ, the NAND circuit 13 after the 16th time point has passed.
The output changes to rLJ, and this output becomes the output of the pulse generation circuit.

The data output X-X5 at the next time point t becomes the same output as at time point 11, so the output of the pulse generation circuit changes to rHJ as at time point 11.

In this way, after t, the same data output as after t1 is repeated, so the output of the pulse generation circuit generates one negative pulse for every six clock signals.

In this embodiment, three flip-flop circuits and one N
By using an AND circuit, 1 [+-! ] I was able to manufacture a pulse generation circuit that generates a negative pulse. To generate the same pulse using a conventional pulse generating circuit, five flip-flop circuits and one NOR circuit are required. Furthermore, this NO
Since the R circuit has five input terminals, the number of wires is considerably large.

It can be seen that the pulse generation circuit of this example was able to significantly reduce the number of wires and elements compared to the conventional example.

Furthermore, two examples are shown below as application examples.

The first example is an application of the embodiment shown in FIG. 3, where the inverted output terminal of the flip-flop 22 and the NA
By changing the connection with the input terminal of the ND circuit 24 to the connection between the inverted output terminal of the flip-flop 21 and the input terminal of the NAND circuit 24, the clock signal has a width of 2 clock signal pulses and a period of 6 clocks. It generates pulses. This application example is shown in Figures 5 and 6 (a) to (
g).

The second example has 4 flip-flop circuits and 2 NA
An ND circuit is used to generate two pulses with different phases and a period equal to eight clocks of the clock signal. Examples of this application are shown in FIGS. 7 and 8(a)-('').

In addition to these two application examples, a desired pulse signal can be generated by adjusting the number of flip-flop circuits, the number of NAND circuits, and the connection method between the output terminal of the flip-flop circuit and the input terminal of the NAND circuit. be able to.

In the embodiment, initialization at power-on was not discussed, but if initialization is necessary, SET/R
A flip-flop circuit with an ESET function may be used.

〔Effect of the invention〕

With the pulse generating circuit according to the present invention, the number of wiring lines and the number of elements can be significantly reduced compared to the conventional circuit, so it is possible to manufacture a circuit that occupies a small area and has low power consumption. Also, if the occupied area is small, the wiring can be shortened, which improves speed performance. Furthermore, a desired pulse signal can be generated by arbitrarily extracting signals from the output terminals of a plurality of flip-flop circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a pulse generating circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of this embodiment, FIG. 3 is a circuit diagram of a pulse generating circuit according to an embodiment of the present invention, and FIG. Figure 5 is a waveform diagram showing the operation of this embodiment, Figure 5 is a circuit diagram of a pulse generation circuit according to an application example of the present invention, Figure 6 is a waveform diagram showing the operation of this application example, and Figure 7 is a waveform diagram showing the operation of this application example. A circuit diagram of the pulse generation circuit of the application example, FIG. 8 is a waveform diagram showing the operation of this application example, FIG. 9 is a circuit diagram of the pulse generation circuit of the conventional example of the present invention, and FIG. 10 is the operation of this conventional example. FIG. 11...Flip-flop circuit, 12...Flip-flop circuit, 13...NAND circuit.

Claims (1)

[Claims] 1. A plurality of flip-flop circuits are connected in series, and the inverted output of the final stage flip-flop circuit is connected to the first stage flip-flop circuit, and two or more of the flip-flop circuits are connected in series. The output or the inverted output of the flip-flop circuit is used as an input to a basic logic gate or a combination of basic logic gates, and the output from this basic logic gate or combination of basic logic gates is used as the output of the entire pulse generation circuit. Pulse generation circuit. 2. The pulse generating circuit according to claim 1, wherein the outputs or inverted outputs of two adjacent flip-flop circuits are input to a basic logic gate or a combination of basic logic gates. 3. The pulse according to claim 1, wherein the period of the pulse pattern obtained when N flip-flop circuits are used is (N×2) times the period of the clock signal applied to the flip-flop circuit. generation circuit.