JPH031233A - Pipeline control system information processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of the parallel processing of a program by making access to an address conversion table with plural processing circuits. CONSTITUTION:The processor is composed in such a manner that an input/ output port is connected to each of processing circuits 1-4, respectively, and a multiple port memory 8 in which the address conversion table 8c is stored is provided, and access to the address conversion table 8c can be performed by the processing circuits 1-4 simultaneously. An instruction real address and a data real address are read out simultaneously by the multiple port memory 8 even when an instruction logic address from the processing circuit 1 for instruction readout and the data logic address of the processing circuit 3 for operand readout are accessed simultaneously. In such a manner, it is possible to operate the processing circuit 1 for instruction readout and the processing circuit 3 for operand read-out simultaneously, and to improve the efficiency of the parallel processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information processing apparatus using a pipeline control method that efficiently utilizes memory and speeds up data processing.

(Prior art) In pipeline control, instruction data is divided into a plurality of parts, and each processing circuit corresponding to each divided part processes each part sequentially at different times according to the processing order. do. On the other hand, a processing circuit among the processing circuits that is not used for processing the instruction data processes other instruction data. This allows parallel processing of a plurality of command data to speed up data processing.

FIG. 2 is a block diagram showing seven examples of conventional pipeline control type information processing devices.

The illustrated device comprises an instruction reading processing circuit 1, a decoding processing circuit 2, an operand reading processing circuit 3, an arithmetic execution processing circuit 4, and the like.

The instruction reading processing circuit 1 is for reading instruction codes stored in a predetermined area of the memory 6. To perform this reading, first, the instruction logical address in which the instruction code is stored is output to the address conversion table 5. Then, the actual instruction address is obtained, and the target command is read from the memory 6 using this actual instruction address.

The decoding processing circuit 2 is for decoding the command read by the instruction reading processing circuit 1.

The operand read processing circuit 3 is for reading numerical data specified by the operand of the instruction data from the memory 6. To perform this reading, first, the data logical address given to the operand is output to the address conversion table 5. Then, a data real address is obtained, and numerical data is read from the memory 6 to the arithmetic execution processing circuit 4 using this data real address.

The arithmetic execution processing circuit 4 processes data read from the memory 6 in accordance with commands read from the memory 6.

The illustrated device also includes an address translation table 5 dedicated to the instruction read processing circuit 1 and an address translation table 5' dedicated to the operand read processing circuit 3.

FIG. 3 is a time chart illustrating the operation of the information processing apparatus described above.

The above-mentioned instruction reading processing circuit 1, decoding processing circuit 2,
The operand read processing circuit 3 and the operation execution processing circuit 4 operate sequentially on one instruction data.

That is, instruction reading, decoding, operand reading, and operation execution are sequentially performed on the instruction data 31. When the instruction reading processing circuit 1 finishes reading the instruction for the instruction data 31, the instruction reading processing circuit 1 reads the next instruction data 32. Therefore, the instruction reading processing circuit 1 and the decoding processing circuit 2 operate simultaneously, and the decoding of the instruction of the instruction data 31 and the reading of the instruction of the instruction data 32 are performed simultaneously. In this way, parallel processing of programs is performed.

Similarly, operand reading of instruction data 31, instruction decoding of instruction data 32, and instruction reading of instruction data 33 are performed in parallel.

FIG. 4 is a block diagram showing another example of a conventional information processing device.

The illustrated device includes only one address translation table 5. Access to this address translation table 5 is exclusively controlled by the arbitration circuit 7. The other configurations are the same as the example shown in FIG.

(Problems to be Solved by the Invention) However, the pipeline control type information processing apparatus having the above configuration has the following problems.

That is, in order to perform parallel processing of programs, the example shown in FIG. 2 requires two address conversion tables for converting logical addresses into real addresses, one for reading instructions and one for reading operands. As a result, the memory capacity for the table becomes large, and there are also drawbacks such as having the same entry twice for instructions and operands.

Further, as shown in FIG. 4, when there is only one address translation table 5, the arbitration circuit 7 determines whether access to the address translation table 5 is an instruction logical address access or a data logical address access. Ru. Therefore, the instruction reading processing circuit 1 and the operand reading processing circuit 3 could not operate simultaneously.

That is, the efficiency of parallel processing of programs may be reduced.

The present invention has been made with attention to the above points, and an object of the present invention is to provide an information processing device using a pipeline control method that reduces the memory capacity for address translation tables and improves the efficiency of parallel processing. It is something to do.

(Means for Solving the Problems) An information processing device using a pipeline control method according to the present invention divides instruction data into a plurality of parts, and each part is processed by each processing circuit corresponding to each divided part. Processing is performed with address conversion at sequential times according to the processing order, and processing of other data is performed by processing circuits that are not used for processing the instruction data among the processing circuits. A pipeline system for parallel processing of instruction data, wherein each of the processing circuits is connected to an input/output port and includes a multi-port memory storing an address conversion table, and each of the processing circuits has a multi-port memory connected to the corresponding address. This system is characterized in that the conversion tables can be accessed simultaneously.

(Function) In the above device, even if the instruction logical address from the instruction read processing circuit 1 and the data logical address of the operand read processing circuit 3 are accessed simultaneously in FIG. 8, the instruction real address and data real address are read simultaneously. Therefore, the instruction read processing circuit 1 and the operand read processing circuit 3 can operate simultaneously, and the efficiency of parallel processing can be improved.

(Embodiment) FIG. 1 is a block diagram showing the configuration of an information processing apparatus using a pipeline control method according to the present invention.

The illustrated device includes an instruction reading processing circuit 1, a decoding processing circuit 2, an operand reading processing circuit 3, an arithmetic execution processing circuit 4, a multi-port memory 8, and the like.

The instruction reading processing circuit 1 is for reading instruction codes stored in a predetermined area of the memory 6. To perform this reading, first, the instruction logical address in which the instruction code is stored is output to the multi-port memory 8. Then, the actual instruction address is obtained from the address conversion table 8c stored in the multi-port memory 8, and the target command is read from the memory 6 using this actual instruction address.

The decoding processing circuit 2 is for decoding the command read by the instruction reading processing circuit 1.

The operand read processing circuit 3 is for reading numerical data specified by the operand of the instruction data from the memory 6. To perform this reading, first, the data logical address given to the operand is output to the multi-port memory 8. Then, the data real address is determined using the address conversion table 8C stored in the multi-port memory 8, and from this data real address,
Numerical data is read from the memory 6 to the processing circuit 4 for execution of calculations.

The calculation execution processing circuit 4 processes the numerical data read from the memory 6 in accordance with the command read from the memory 6.

The multi-port memory 8 consists of a random access memory, ie a so-called 2-bot RAM, which can be accessed by two processing circuits. This multi-port memory 8 stores an address conversion table 8C. One input terminal 8a of the multi-port memory 8 is connected to the instruction reading processing circuit 1, and the other input terminal 8b is connected to the operand reading processing circuit 3. The output terminal 8a corresponding to the input terminal 8a of the multi-port memory 8 is returned to the instruction reading processing circuit 1, and the output terminal 8b' corresponding to the input terminal 8b is returned to the operand reading processing circuit 3. There is.

Next, the operation of the pipeline control type information processing apparatus configured as described above will be explained with reference to FIGS. 1 and 3.

First, when execution of the instruction data 31 is started, the instruction read processing circuit 1 operates. The instruction read processing circuit 1 outputs an instruction logical address to the multi-port memory 8 storing an address conversion table 8C, and obtains an instruction actual address from the address conversion table 8c. Then, the instruction read processing circuit 1 reads the command from the memory 6 using the obtained instruction actual address.

Next, when the reading of the command for the instruction data 31 is completed, the decoding processing circuit 2 operates, and the decoding processing circuit 2 decodes the command for the instruction data 31. At the same time, the instruction reading for the instruction data 32 is performed in the same way as the instruction reading for the instruction data 31.

When these processes are completed, the next land read processing circuit 3 operates. The operand read processing circuit 3 is
The data logical address for the instruction data 31 is output to the address conversion table 8C, and the data actual address is determined by the address conversion table 8C. Then, the operand read processing circuit 31 reads the corresponding numerical data from the memory 6 using the obtained data real address.

At the same time, the command for the command data 32 is decoded in the same manner as for the command data 32. Further, at the same time, the instruction reading for the instruction data 33 is performed in the same manner as the instruction reading for the instruction data 31 and 32.

In this case, the data logical address for the instruction data 31 and the instruction data 33 are stored in the address conversion table 8C.
The instruction logical address for is input at the same time, but
Since the address conversion table 8C is stored in the multi-port memory 8, the data real address for the instruction data 31 and the instruction real address for the instruction data 33 are obtained at the same time. Therefore, the instruction reading processing circuit 1 and
The operand read processing circuit 3 can operate simultaneously. As a result, parallel processing of the instruction data 31 and the instruction data 33 is not hindered.

When these processes are completed, the operation of the arithmetic processing circuit 4 starts next. The arithmetic processing circuit 4 performs arithmetic processing on the numerical data read out by the operand readout processing circuit 3 in accordance with the command regarding the instruction data 31 read out by the instruction readout processing circuit 1 . At the same time, the operand reading processing circuit 3 reads the operand for the instruction data 32, and the decoding processing circuit 2
The command for the instruction data 33 is decoded, and the instruction reading processing circuit 1 reads the instruction for the instruction data 34. In this case, as in the case described above, operand reading and instruction reading are performed simultaneously using one address conversion table 8C.

Thereafter, the execution of instruction data 32 to 34 is completed in the same manner as the execution of instruction data 31.

The invention is not limited to the embodiments described above.

That is, in the above-mentioned embodiment, a case has been described in which the address conversion table 8c can be accessed simultaneously by two processing circuits, but the present invention is not limited to this. 3
If there are more than two, the address conversion table 8C may be stored in a multi-port memory having three or more ports so that it can be accessed simultaneously by three or more processing circuits.

(Effects of the Invention) As explained above, the pipeline control type information processing device of the present invention allows a plurality of processing circuits to access the address translation table. Compared to the conventional example in which a plurality of address conversion tables are provided, the memory capacity can be significantly reduced while maintaining the same effect. Furthermore, as shown in FIG. 4, compared to the conventional example in which access to the address translation table is arbitrated by an arbitration circuit, even when there are multiple processing circuits that access the address translation table, these processing circuits are can operate simultaneously. Therefore, the efficiency of parallel processing of programs can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing device using a pipeline control method according to the present invention, FIG. 2 is a block diagram showing the configuration of an example of an information processing device using a conventional pipeline control method, and FIG. FIG. 4 is a time chart of data processing procedures in a line control type information processing apparatus. FIG. 4 is a block diagram showing the configuration of another example of a conventional pipeline control type information processing apparatus. 1... Processing circuit for reading instructions, 2... Processing circuit for decoding, 3... Processing circuit for reading operands, 4... Processing circuit for executing operations, 8... Multi-port memory, 8c...・Address conversion table.

Claims (1)

[Claims] Instruction data is divided into a plurality of parts, and each processing circuit corresponding to each divided part processes each part sequentially at different times according to the processing order with address conversion. On the other hand, in a method using a pipeline method in which a plurality of instruction data are processed in parallel by processing other data using a processing circuit that is not used for processing the instruction data among the processing circuits. , comprising a multi-port memory in which an input/output port is connected to each of the processing circuits and an address conversion table is stored, so that each of the processing circuits can access the address conversion table simultaneously. An information processing device using pipeline control method.