JPH03128476A - Driver circuit with test mode - Google Patents

Abstract

PURPOSE:To enable accurate inspection without element breakage even if a short circuit is caused owing to a conductor defect by providing a switch circuit which outputs a signal of logic level by switching based upon a test mode signal. CONSTITUTION:A switch circuit 3 is provided on the input side of the driver circuit which is constituted by connecting a C-MOS transistor(TR) 2 consisting of a P channel MOSTR Q1 and an N channel MOSTR Q4 is connected in parallel in front of a resistance bias type basic Bi-COMS logic circuit 1, and the circuit 3 is provided with a test mode terminal TM. This constitution operates as a logic circuit when a terminal TM is at H. When the terminal TM is held at L, an input terminal IN is at L and an output terminal is at H; when the terminal IN is at H, high impedance is obtained at the output terminal. Consequently, logic L or H is applied to respective conductors of a printed wiring board while the terminal TM is placed in a state of logic L and then the output logic L of the conductors changes into logic H because of a short-circuit defect, so that the abnormality can be detected.

Description

[Detailed description of the invention] 〔table of contents〕 overview.

Industrial field of application Conventional technology (Fig. 3) Means for solving the problems to be solved by the invention (Fig. 1) Working examples (Fig. 2) Effects of the invention [Summary] Driver with test mode Regarding circuits, the purpose of this test is to enable accurate testing without causing element destruction even if a short circuit occurs due to wiring defects when testing wiring defects on printed wiring boards equipped with LSI etc. Basic resistance bias type B'+
- In a driver circuit in which C-MOS transistors are connected in parallel at the front stage of a CMOS logic circuit, there is a logic circuit on the input side of the C-MOS transistor that forces the output of the driver circuit to be high impedance by switching with a test mode signal. It is configured to connect a switch circuit that outputs a level signal.

[Industrial application field]

The present invention relates to a driver circuit with a test mode, and more specifically, to an LSI using the driver circuit according to the present invention.
It is used to perform tests on printed wiring boards mounted with other LSIs, etc., to check whether the wiring has been done correctly on the printed wiring board during manufacturing, and in particular to prevent element destruction during testing. This invention relates to a driver circuit with a test mode.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example, in which (A) shows a basic resistance bias type B i -CMOS logic circuit, and (B) shows a resistance bias type improved B i -CMOS logic circuit. CM
It is a diagram showing an OS logic circuit.

In the figure, Ql and Q2 are P-channel MO3I-transistors, Q4 and Q5 are N-channel MOS transistors, and Q3
, Q6 is a bipolar transistor, IN is an input terminal, O
UT is the output terminal, VCI (H) is the power supply (high level),
VC2 (L) is a power supply (low level), and R is a resistance.

(A) The basic i-CMOS logic circuit shown in the figure is
This is a basic circuit of a resistance bias type Bi CMOS driver circuit.

MOS transistors Q7 and Q5 operate to bias bipolar transistors Q3 and Q6.

The operation of this circuit is as follows: When a high level signal rl (J is input to the input terminal IN, MO3I transistor Q2 is turned off, MO3I transistor Q5 is turned on, bipolar transistor Q3 is turned off, bipolar transistor Q6 is turned on, and the input terminal When a low level signal "L" is input to IN, transistors Q2 and Q3 are turned on and transistors Q5 and Q6 are turned off.

Therefore, when the input terminal IN is "H", the output terminal OU
T is "L" and when IN is "S", OUT is "H".

However, the above basic circuit has the drawback that in steady state, the output is 0 [JT is in a high impedance state.
When used as a driver circuit, there is a problem with noise.

For example, by applying r L J to IN, transistor Q2
When transistor Q3 is turned on, even if transistor Q3 turns on in a transient state, the base-emitter voltage of transistor Q3 cannot be maintained sufficiently in steady state, transistor Q3 turns off, and the output becomes high impedance. become.

An improved Bi-CMO3 logic circuit as shown in FIG. 3(B) is known as a circuit that solves these drawbacks.

This circuit has a P-channel M
CMOS transistors consisting of an OS transistor Q1 and an N-channel MOS transistor Q4 are connected in parallel.

In this circuit, a signal applied to the input terminal (N) is logically inverted and current amplified, and then transmitted to the output terminal OUT.

That is, when the human power is logic rH, transistors Q1 and Q2
is turned off, and transistors Q4 and Q5 are turned on.

At the same time, transistor Q3 is turned off, transistor Q6 is turned on, and the output becomes logic "L". On the other hand, human power is logic “L”
In the case of , the above-mentioned on and off states are reversed and the output becomes logic rH.

Here, as described above, transistors Q2 and Q5 operate to bias transistors Q3 and Q6, and transistors Q1 and Q4 function to maintain low impedance in a steady state of output. That is, when the transistor is on, the transistor Q1 is turned on by the transistor Q2.
The impedance of the transistor Q4 is lower than that of a series circuit of a transistor Q5 and a resistor R, and the transistor Q4 functions to have a lower impedance than a series circuit of a transistor Q5 and a resistor R.

Note that although the figure shows a case where one each of transistors Q1 to Q6 is used, it is common to connect multiple transistors in parallel to match the characteristic impedance of the transmission path connected to the output. be.

In this way, the logic level of the output is determined by the transistor Q
This is guaranteed by turning on 1 to Q3 or Q4 to Q6.

[Problem 8 to be solved by the invention] The conventional device as described above had the following drawbacks.

(1) Printed wiring boards on which LSIs using conventional logic circuits (driver circuits) as described above and other LSIs are mounted are tested to see if they are correctly wired at the time of manufacture.

At that time, if a short circuit occurs due to a wiring defect on the printed wiring board, an excessive current flows from the high level rH output to the low level LJ output (because the current drive capability is large), causing elements such as transistors to flow. There is a risk of destruction.

(2) In recent years, the wiring density of substrates on which LSIs and the like are mounted has become higher. In addition, the number of pins in LSI packages has increased, making it difficult to easily detect wiring defects on boards.

For this reason, it is difficult to prevent element destruction during testing as described above.

The present invention eliminates these conventional drawbacks, and even when a short circuit occurs due to a wiring defect when testing for wiring defects on a printed wiring board equipped with a 31, etc., it is possible to accurately test the wiring without causing element damage. The purpose is to enable accurate inspections.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention, and the same reference numerals as in FIG. 3 indicate the same parts. In addition, ■ is the basic i-CMOS logic circuit of the resistance bias type, 2 is a C-MOS transistor, 3 is a switch circuit, Sl and S7 are switches, and T
M indicates a test mode terminal.

The present invention provides P-channel MOS transistors Q2, N
A P-channel MOS transistor Q5 and a resistor bias type basic i-CMO3 logic circuit stage consisting of a channel MOS transistor Q5 and bipolar transistors Q3 and Q6 are used.
A switch circuit 3 is provided at the input end of a driver circuit in which C-MO3I-transistors 2 each consisting of an S transistor Q1 and an N-channel MOS transistor Q4 are connected in parallel.
This switch circuit is provided with a test mode terminal TM.

The basic logic above is as follows: In the i-CMO3 logic circuit stage,
The driver circuit in which the C-MOS I-transistors 2 are connected in parallel is the same as that shown in FIG. 3(B), and a test mode terminal TM is provided separately from the input terminal IN of this driver circuit, and 3, switch S1 and S2.

High level signal rH to test mode terminal TM.

When input, switch S1 of switch circuit 3 closes,
S2 opens.

This state is the same as the conventional circuit shown in FIG. 3(B), and the input terminal IN is at high level rH.

At this time, the output terminal OUT is at a low level, and if the input terminal IN is at a low level, the output terminal OUT is at a high level.

Further, if the test mode terminal TM is "L", the switch S1 of the switch circuit 3 is open and the switch SZ is closed.

In this state, the gate voltages of the transistors Q4 and Q5 are disconnected from the input terminal TN, and the logic "L" of the power source VC2(L) is forced by the switch S2.

Therefore, the output becomes high impedance because transistors Q4, Q5, and Q6 are turned off. At this time, if the input terminal is "L", the output is rH, which is the same as in the conventional example.

[Effect]

Since the present invention is configured as described above, if the test mode terminal TM is "rH", it operates as a logic circuit similar to the conventional example, and if the test mode terminal TM is "L", the output is forcibly set to high impedance. Become.

That is, if TM is set to "L", the input terminal IN becomes r1. , the output terminal becomes "11", and the input terminal I
When the output terminal becomes high impedance, the output terminal becomes high impedance.

Therefore, by keeping the test mode terminal TM in the logic "L" state and applying logic "L" or "logic 1" to each wiring on the printed wiring board, the output logic "L" can be set in the wiring with the short-circuit defect. changes to the logic "+-IJ", making it possible to detect an abnormality.

Moreover, even if a short circuit occurs at this time, since the output is high impedance, a large current will not flow through the transistor, thereby preventing element destruction.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a circuit diagram of one embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts. In addition, G1 is an inverter, G7 and Q9 are N-channel MOS transistors,
G8 indicates a P-channel MOS transistor.

In this embodiment, a transmission gate consisting of transistors Q7 and G8 is used as the switch S1 of the switch circuit 3, and a transistor Q9 is used as the switch Sz.
The other circuits are the same as the conventional example.

When the test mode terminal TM is at the logic "■4", transistor 79 is on and the output of the inverter Gt is at the logic "L".
'', transistor QB is turned on and transistor Q9 is turned off.

This state is functionally exactly the same as the circuit of FIG. 3(B).

Next, when TM is logic "L", transistors Q7 and G8
is off, Q9 is on, and transistors Q4 and G5
The input of is disconnected from input terminal IN.

Then, the transistor Q9 forces the logic “L”.
is input, and the output becomes high impedance because transistors Q4, G5, and G6 are turned off. In this state, the input terminal IN is "L" and the output terminal OUT is "N".
The state of ( ) is the same as in the conventional example.

Further, a pull-down resistor is connected between the output terminal OtJT and the input terminal IN of the next stage (connected by wiring on the board) to ensure the logic level.

As shown above, an LSI etc. using a driver circuit consisting of an i-CMO3 logic circuit is mounted and wired on a printed wiring board, and in order to test whether or not this printed wiring board is correctly wired, a test is required. Mode terminal TM
is set to logic "L".

At this time, the output [Ll is in a high impedance state, so even if a short circuit occurs and rHJ and ``SHI'' are connected, a large current will not flow and destruction of elements such as transistors can be prevented.

In this way, by applying logic "L" or logic "11" to each wiring on the board while preventing element destruction, the output logic rL in the wiring with the short-circuit defect changes to logic rHJ. This makes it possible to detect abnormalities.

After the test, when using it as a normal driver circuit, apply logic rH, fixedly to the test mode terminal TM, turn on transistor 79 and G8, and turn on transistor Q.
9 can be turned off, it can be used as the same circuit as a conventional driver circuit.

〔Effect of the invention〕

As explained above, according to the present invention, when carrying out a test to determine whether or not a printed wiring board on which an LSI or the like using a driver circuit made of a Bi-CMO3 logic circuit is mounted and wired is correctly wired, By applying a predetermined logic level signal to the test mode terminal, wiring defects can be easily detected, and even if a short circuit occurs due to incorrect wiring, damage to elements such as transistors can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a driver circuit with a test mode according to the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional example. 1-Basic i-CMO3 logic circuit 2-CM OS I-Run raster 3-Switch circuit 1” M---Test mode terminal

Claims (1)

[Claims] Basic resistance bias type Bi-CMOS logic circuit (
In a driver circuit in which a C-MOS transistor (2) is connected in parallel in the preceding stage of 1), the output of the driver circuit is forced to the input side of the C-MOS transistor (2) by switching with a test mode signal. A driver circuit with a test mode, characterized in that a switch circuit (3) is connected that outputs a logic level signal to make the impedance high.