JPH0312871A - PCM signal recording and reproducing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on the pct (pulse code modification ii1.il) 1
．． Regarding the W-recording and reproducing device, especially the Komaki Nyu (LP)
) mode suitable for a rotary head type PCM recorder.

[Prior Art] There is a DAT (Digital Audio Tape Recorder) as a rotating head type PCM recorder.
In addition to the recording and playback mode of bit@line doji PCM signals,
Sampling frequency e62IcIi2.12 bit fold MA'! !
There is a long-time H self-recording and playback mode (hereinafter referred to as LP mode) using ik child P CM ik. This reduces the number of sampling cycles and the number of bits of the transmitted sample tape by half, and reduces the tape feed speed by half, thereby reducing the track pattern and data h You can essentially double the recording and playback time without changing the recording density.

In conventional devices, a data conversion circuit is added to the input/output part of the P C,'M No. 41 as described in %υi Publication No. 61-96574. ”1987
June (The 1) AT Conjertnct'
DIGITAL AUDIOTA PERECORDERS
A RAM (random access memory) address generation circuit that follows the LP mode interleave format described in YSTEM 'June 1987) is provided,
LP mode was realized.

[Problem to be solved by the invention]

In the above-mentioned prior art, a data conversion circuit for realizing the LP mode is required for each of the input section and the output section of recording and reproduction data, and one path and operation timing are complicated. For this reason, it was an extension to add a data conversion side 125 compatible with the LP mode to the conventional individual processing circuit (LSI) dedicated to the standard mode to realize LP Shinryu. In addition, consideration has been given to the circuit that processes interleaving in LP mode, but two RAM address generation circuits are required to handle interleaving between LP mode and standard mode, making the circuit scale large and complicated. It had become. Moreover, that's not all (, LP mode interleaving is the upper level of different channel data,
This is a format in which the lower bits together constitute one piece of sample data, and there is a problem in that uncorrectable data is scattered during playback, and conventional interpolation processing does not work properly.

The purpose of the present invention is to provide a data conversion circuit compatible with LP mode that can be externally connected to a 9th signal processing circuit designed exclusively for standard mode, and a flag processing circuit that enables the same interpolation processing in both standard and LP modes. The object of the present invention is to easily realize long-time recording and playback in accordance with the LP mode format by providing a RAM address generation circuit that can be used in both modes.

[Means to solve the problem]

The purpose of the above ia is to convert the data conversion circuit into a one-time processing circuit (LSI
) and the RAM, the data conversion circuit must replace and delay the upper 4 bits and lower 4 bits of sample data in a non-chronological order, and each issue processing circuit ( The access timing of bus data input and output to RAM for AD conversion (analog-to-digital conversion) and DA conversion (digital-to-analog replacement) is the same in both LP mode and standard mode.
A.D.

The number of times RAM is accessed as data for DA conversion processing is thinned out once every two circles, the encoding of the correction code, the number of times the code processing is thinned out twice out of every four times, tape running, cylinder The number of revolutions is set to half that of the standard mode, and during playback, multiple flags for the same sample corrected with different sample series are compared, and the most affected flag is selected or generated for each sample. This is achieved by outputting one 7-lag signal corresponding to the data.

[Effect]

When the data conversion circuit operates in standard mode, data is simply passed through without being converted. Also, in LP mode,
The tape feed speed, cylinder rotation speed, and main recording/reproducing frequency are half of those in standard mode, and the input/output data timing of the digital signal processing circuit (LSI) path is the same in LP mode as in standard mode (5840 samples, 71 revolutions). The data conversion circuit performs predetermined data conversion corresponding to LP mode interleaving, and the RAM is accessed once every two times (2880 samples and 71 rotations), and the LP mode interleaving RAM address generation circuit is as described above. It is controlled to correspond to RAM access, and the flag processing circuit selects the flag with the worse interpolation 7 lag distributed by LP interleaving and data conversion during playback, and outputs each digital signal at the same timing as in the standard mode. input to the processing circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a digital signal processing circuit that controls recording and playback, 2 is a data conversion circuit that supports LP mode, 5 is RAM, 4 is an AD/R candidate circuit, 5 is a DA conversion circuit, 6 is a waveform, etc. 7 is a servo circuit that primarily controls tape running and cylinder rotation; 71 is a reel motor driver 72 is a cylinder motor driver 7
5 is the capstan motor, dry huff 4 is the reel motor,
175 is a cylinder motor, 76 is a capstan motor,
81 is a recording amplifier, 82 is a playback amplifier, 85 is a recording/playback switch, 9 is a cylinder, 91 and 92 are magnetic heads 95 are capstans, 94 is a reel, 95 is a magnetic tape, Ll and R1 are left and right channel audio. No. 1g input terminals, LO and RO, are left and right channel audio output terminals. Operation during recording is input terminal LI.

The audio signal input from R1 is sent to the AD conversion circuit 4, where it is converted into digital data of the R2 channel, and the digital signal processing circuit 1 generates a correction code and performs interleave processing. These processes are performed using the RAM 3, but at this time, in the standard mode, the data conversion circuit 2 only operates to pass through the data without converting it, and in the LP mode only The data is converted into a non-aligned data output that supports 12-bit data compression and LP mode interleaving. Further, the digital signal processing circuit 1 adds a subcode number and modulates the signal, outputs a recording signal at half the standard transmission rate during LP, and outputs the recording signal to the tape via the recording amplifier 81 and then to the magnetic heads 91 and 92. 95 in track units. The rotational speed of the tape ih and the cylinder is controlled by the servo circuit 7 so that it is half of the standard mode in the LP mode during both recording and playback. In the playback operation, the playback signal that has one transmission rate in the standard mode during LP is passed through the playback amplifier 82, subjected to waveform shaping in the data signal processing circuit 6, and subjected to clock recovery and data extraction, and then sent to the digital signal processing circuit. 1 performs error correction and data processing. At this time, the data conversion circuit 2 passes the data without performing any data conversion in the standard mode. In addition, the data conversion circuit 2 performs inverse conversion during AD recording only during LP, that is, data array conversion corresponding to nine interleave to form 12-bit data, performs decompression processing to 13-bit data, and performs correction processing. Output flags indicating the results in chronological order13
It is processed to correspond to bit PCM data.

Furthermore, for the uncorrectable data in the digital clock 6 processing circuit 1, based on the processed flag signal, the nl value is maintained or interpolation processing is performed using the average value, and the DAg conversion circuit 5 restores the original L (left), R (Right) Outputs 2-channel audio signals.

Next, the operation of the apparatus according to the present invention will be explained in accordance with the timing diagrams shown in FIGS. 2 through 4.

FIG. 2 shows the standard mode operation timing for manufacturing according to the present invention. In the figure, (1) is a frame φ signal for insulting the frame (one frame consists of two tracks of signals)
, (2) is a reproduction or recording signal for each track, and (5) is a timing signal for generating an error correction code.
AT uses a doubly encoded Reed-Solomon code (hereinafter referred to as C, C2 code). Also, (4
) is a 4g signal indicating the timing to fold AD-converted data into RAM, (5) is a signal indicating the timing to fold reproduced data into RAMK, (6) is a signal indicating the error correction processing timing by ClIC2 code, (7) is RAM
This is a signal indicating the timing of reading out error-corrected data from the DA, converting it to DA, and outputting it. (8) is a reset signal for a circuit that generates a RAM address for interleaving.

When the diameter of the cylinder 9 in Fig. 1 is 30φ, the cylinder rotation speed in the standard mode is 2000 rotations/rotation button The transmission frequency for recording and playback is 9.408 Jlz, and the cylinder 1
The period of rotation is 50 m5ec, and 11 is the period of one rotation of the cylinder in Fig. 2.

The cylinder is rotated by the servo circuit 7.

Both phase and phase are synchronized with the frame φ value number, and recording and reproduction signals are generated at the timing shown in Figure 2 (2). In the figure,
A and B are Usuki records and Nyu data by the magnetic heads 91 and 92 shown in FIG. 1, where the magnetic head 91 has a + (plus) azimuth angle and the magnetic head 92 has a - (minus) azimuth angle. It has an angular shape. The regenerated A and H signals are sent to the RAM I/C at the timing shown in (5).
At timing (6), error correction is not performed on track-by-track basis from the RAM data that has been inserted and filled in. At timing (7), the data read from RAM in the j1 sequence of deinterleaving is DAl& exchanged. Output audio data. During recording, the audio signal input at the timing of
Generate C, , C2 codes for each track from υdeday (
6) If no, output and record the PCM numbers of A' and B' for each track. In DAT, interleaving is 2
Track (1 frame) optical connection, interleak and gain interleap circuit t with reset signal shown in (8)
set. The configuration of the RAM is such that one frame of data for AD and DA input/output and one frame of data for encoding processing are used by switching RAM banks.

Next, FIG. 6 is a timing diagram of the LP mode recording operation of the apparatus according to the present invention. In FIG. 2, the ``-''-name signal is a ``timing'' signal representing a four-movement.

When recording in LP mode, the cylinder phase 9 rotation speed is synchronized at the timing of the double period of the frame φ signal ((SO77Lεec)), and the tape feeding movement and recording The data transmission frequency is half of the standard time.One frame during LP is 60 eC, and according to the timing of (5), the sampling frequency is ?5.i!□2, and the R channel data is A.
D-convert the data, compress it to 12 bits (13 bits per sample data), and store it in RAM according to the interleave for LP.
Soak it in. The number of samples to be loaded into RAM at this point is 6.
Between oms'gc, 6Qmsec x 52KHz
X 2ch X-! ! -== 2880 samples and 6 sampling frequency 4BIJz 1 frame of standard time (
50m5tc x 48KBZ x 2ch =-28
80), and the sampling frequency is 48ff in timing.
Experiment by performing a RAM access that is thinned out once every two times in the Z standard mode. Note that the details of the timing and the method for realizing interleaving will be explained later.

The data inserted into RAMK is (timing 0 to 6)
For example, the '1 # Cz code for each track is generated using timings A and d2 out of the four times, and the code generation process or RAM loading process is stopped at the remaining timings α and C. The encoded data is subjected to the same processing as in standard time by the digital No. 48 processing circuit 1,
A', B' at half transmission rate (4,704MHz)
The signal is output as a recording signal as shown at the timing shown in FIG.

FIG. 4 is a reproduction timing diagram in the LP mode of the apparatus according to the present invention.

In FIG. 4, the same signal names as in FIG. 2, 2m5 are timing signals representing the same operations.

During playback in LP mode, synchronize the phase and rotational speed of the cylinder at the timing of double the period of frame φ (60 m5ec), and reduce the tape feed speed by half (1000 revolutions/minute), as shown in (ri). , the transmission frequency mantissa of the obtained reproduced signal is half of the standard time (4,7041MHz
). Therefore, the digital 48 signal processing circuit 1 in FIG.
The reproduced data of A and H, which are controlled to operate at Hz and *tuned, are stored in the RAM in real-time processing as shown in Fig. Among the processing timings, for example, at j, h or g, y, a correction operation using C, C, code is performed, and at timing (6), the data is extracted from the RAM in the order of deinterleaving, The data conversion circuit 2 in Figure 1 rearranges the data 12.
Construct the bit data, expand it to 13 bit data, and
A convert.

Next, a data conversion circuit according to the present invention will be explained with reference to FIG.

In Figure 5, x-Y is the data path, and X is the RA
The side connected to M is the side connected to the digital signal processing circuit, and the side Y is connected to the digital signal processing circuit. Further, 21 is a compression circuit, 22 is an array conversion circuit, 25 is an array inversion circuit, 24 is an expansion circuit, 25
is a flag processing circuit, 26 and 27 are output control buffers,
28 is a timing generation circuit.

The output control buffers 26 and 27 are used to prevent data on the bus from being converted in the standard mode (LSI, R in the standard mode).
Control is performed so that the data input/output between the AMs is exactly the same, that is, the input/output data is not converted at all. Specifically, when the RAM is output, the buffer 26 stops outputting, and when the RAM is input, the buffer 27 stops outputting.

Next, the operation of each circuit will be explained. When recording in LP mode, the 13-bit sample data, which is an AD-converted array output from the digital signal processing circuit, is divided into upper and lower 8 bits.
The data is taken bit by bit into the compression circuit 21 and compressed into 13-bit data or 12-bit data.

The data compressed to 12 bits is decomposed into 12 bits by the array conversion circuit 22, rearranged in a non-chronological order in units of 8 bits, and output onto the bus at a predetermined timing to be described later. Of course, at this time, the buffer 26 is controlled to stop outputting, and the converted data is written into the RAM via the bus X.

During playback in Lp mode, the 13-bit sample data for DA conversion output from the RAM on the bus is loaded into the array inversion circuit 23 for each of the upper and lower 8 bits, and the array inversion circuit 22 and the entire (inverse) The data is inversely converted to form an array to form 12-bit data in chronological order.Furthermore, the 12-bit data is decompressed into 13-bit data by the decompression circuit 24.
After that, the data is divided into upper and lower 8-bit data.
u will be u. Then, it is output onto the bus and supplied to the LSI side. Further, when reading the above-described 13-bit sample data for DA conversion from the RAM, the result of correction processing by C1 and C2 corresponding to this sample data is output as a flag. On the other hand, when the data is decomposed and rearranged by the array inversion circuit 25 and outputted from the decompression circuit 24, the above-mentioned one sample data is dispersed into a plurality of sample data, and the data is divided into samples input to the digital signal processing circuit. , the correspondence with the flag will be impaired. Therefore, the flag data 90 processing circuit 25 compares a plurality of 7 lags corresponding to a plurality of pieces of data constituting one sample data outputted from the decompression circuit 24, obtains the worst flag value, and sends it to the decompression circuit. The flag is input to the digital signal processing circuit at a timing corresponding to the data coming out of 24. The digital signal processing circuit performs processing of holding the previous value or interpolating the average value depending on the state of this flag. Incidentally, when the decompression circuit 24 and the 7-lag data processing circuit 25 output data, the buffer 27 is controlled to stop outputting. Further, the timing generation circuit 28 is a circuit that mainly generates timing clocks for operating the above-mentioned circuits and signals for controlling the output of each bus signal. In addition, compression time ll5
21 and the decompression circuit 24 are not the gist of the present invention, so the details of the circuits will be omitted, but
There are 5 circuits that perform the conversion and inverse conversion described in Section 44.

A specific embodiment of the array conversion circuit 22 shown in FIG. 5 is shown in FIG. 6, and its operation will be explained with reference to FIG.

In FIG. 6, the same reference numerals as in FIG. 5 indicate circuits having the same functions and the same contents. Further, 221 to 224 are 1'2 pit latch circuits, 225 is the upper 4 bits of the data bus input to the RAM, and 226 is the lower 4 bits. In FIG. 7, ((ri) is the same signal as the frame 1 signal in FIG. 5.

In addition, (2) is a left and right channel identification signal of AD converted data, (5) is a timing 1 signal representing the area where the digital signal processing circuit outputs the AD converted data to bus Y, and (4) is a bus Y signal. This is Y data, which has been AD converted, and indicates each sample of the R channel. Here, the subscript indicates the upper 8-bit data, and l indicates the lower 8-bit data. In addition, (5) is a signal indicating the latch and compression timing of AD conversion data on bus Y, (6) to (9)
) is the latch data of the 12-bit latch circuits 222 to 224 in FIG. 6, and (10) is a signal indicating the sample data and timing output by the array conversion circuit on bus X.

(11) is a timing 2 signal indicating the timing at which AD-converted data is read into the RAM during LP mode recording. Here, the ADg conversion data output timing of Nox Y shown in (4) is standard mode, sampling frequency 52KH.
AD at the same time as z, that is, the sampling frequency is 48KIIZ
i for the CK signal (a signal similar to the timing 1 signal, but with a different period and duty). This operation is common to both the LP and standard modes, and in the LP mode, data is further compressed and arranged, and the timing and data shown in (10) are stored in the RAM. This is the output control bus α of latch circuits 1221 to 224 in Figure 6.
-d is obtained by controlling the output at the timing shown by the arrows in FIG. ), and the interleaving is completed in a cycle of 7 frames and 1 signal, that is, the RAM address of the AD conversion data is shifted by the timing signal (11). =m in the RAM address generation method for interleaving will be explained later.

A specific example of the array inversion circuit 23 shown in FIG.
The operation will be explained with reference to FIG.

In FIG. 8, the same reference numerals as in FIG. 5 indicate circuits having the same functions and the same contents. Also, 251, 252, 255 are 8
The pit latch circuits 255 and 254 are 13-bit latch circuits, 256 is a 12-bit latch circuit, and 24 is an expansion circuit.

Also, in Fig. 9, (1) is the same as the signal shown in Fig. 4 frame 1 signal (2) is when the RAM is DA during LP mode playback.
A signal indicating the timing to output the data to be converted,
(5) is data on bus X, which is a signal indicating the data to be DA-converted by the RAM and the output timing. (4)～
(7) is the latch data of the latch circuits 261 to 265 in FIG. 8, and (8) is the latch circuit 26 that latches the 12-bit data outputted under the control of the latch circuits 231 to 265.
6 clock.

This is a signal obtained by the logical sum of (2) and (1D) in the same figure.

(9) is a signal indicating the data of the latch circuit 266 and the operation timing of the expansion circuit 24; (11) is a signal indicating the timing of input to the digital signal processing circuit on bus Y and the inversely converted data.

Here, the timing and υ data shown in 149 (2), C5) are the same as the timing and data of accessing the RAM during recording shown in Figure 7 (10) and (11), and during playback, Reads from RAM in 8-bit units and sends upper, lower, and
Latch 8 bits at a time. This data is then delayed by the latch circuits 256-235, and the 4-bit data shown in FIG. 8 A1-D3 is controlled so that it is latched in the latch circuit 266 at the timing shown in FIG. 9 A1-D5. .

Furthermore, the data in the latch circuit 256 is transferred to the decompression circuit 24 and decompressed until the next data is latched, and at the timing shown in No. 91a (11), the upper and lower 8 bits are Output data to bus Y. The direction data is input to the digital signal processing circuit,
This timing and data arrangement are the same as in standard mode.

Next, a tenth embodiment of the flag processing circuit according to the present invention will be described.
This will be explained using figures. In the Lp mode, as shown in Figure 9 (6) (the lower 4 bits of the L and R channels are combined to form 8-bit data, or at a timing when the upper and lower data do not form a pair). Therefore, flag No. 13 representing the result of correction processing using C1, C, and codes is L.

It cannot be made to correspond to each 12-bit sample data of the R channel, and if this flag is used as it is, there is a problem that the interpolation process when correction is impossible will not work properly. The flag processing circuit of the present invention is a circuit that solves this problem.

In FIG. 10, the same reference numerals as in FIG. 5 indicate the same circuits having the same performance. Further, 251 to 254 are latch circuits, 25
5 and 256 are decoding circuits, and 257 is a data selection circuit.

This circuit is a circuit created corresponding to the data inversion circuit with timing operation shown in FIG. 9.

The timing shown in FIG. 9 (4) to (7) and the flag signal corresponding to the data shown in the figure or the latch circuit 2 of FIG.
51 to 254, and generates the flag No. 1g corresponding to the data of (11) in the same figure at the timing shown by the arrow in FIG. The decoding circuit 25 decodes the two flag signals in the second and fourth stages.
5, the selection circuit 257 decodes or compares the data so that it is equal to the incorrect data, and the selection circuit 257 selects the data as shown in FIG.
One flag No. 13 corresponding to the timing shown in 11) and the data shown is output. As a result, the digital signal processing circuit can process the input data and the correction result in a one-to-one correspondence, so that the interpolation operation can be performed normally with the same processing as the standard mode.

Here, the flag data may be output on KusuX in various formats. For example, flags for the number of bits, cl, G', and code as flag data are output independently. Alternatively, 13-bit 1 sample data may be divided into upper and lower parts on 8 pit nodes, and the flags for the upper and lower parts can be output independently, or the upper and lower parts can be combined into one flag. For example, when In any case, in normal operation, the data is decoded in the same order on the RAM in both LP mode and standard mode, and the sample data in LP mode is distributed, so flags for the same sample are output. The signal is dispersed into two or more, and the above-mentioned seven-lag processing circuit is required. Also C1. In the case where the flags for C and the code or the flags for the upper and lower samples are each output independently, this can be handled by using the circuit shown in FIG. In particular, when the flag signal is 1 bit and, for example, alg indicates that it cannot be edited, the decoding circuits 255 and 256 may be logically 0 or 0. For example, if the flag signal is 2 bits, 1 oo 1 error, '01' 1 sample correction '1012 sample correction, 11111fT correct failure, etc. When identifying by code, output two flags A and R (i) as shown in the truth table in Table 1. Decode as shown.

8 Table 1 The formula for 2-bit decoding shown in Table 1 can be obtained as follows.

The data conversion circuit of the present invention described above is suitable for implementation by connecting to the bus between the digital signal processing circuit and the RAM as shown in FIG. The array conversion circuit 22 can be placed in the AD conversion data input section of the digital signal processing circuit or just before the RAM bus. It can be implemented by placing it in the interpolation processing part of the digital signal processing circuit or immediately before the RAM bus.If the data conversion circuit is implemented inside the digital signal processing IP!4 path in this way, the output control buffer shown in Figure 5 Control of bus signal input/output as shown in 26 and 27 becomes easy.

'M: R that realizes interleaving in LP mode.
The AM address generation method will be explained. Figure 11 is DAT
1 is a diagram showing the interleaving of FIG. D A 7' is an interleave completed with 2 tracks, and each track of A and B has 128 blocks (BO to B127).
#bO”b1!?) consists of PCM signals.

In the figure, C' is an area where 02 parity data for error correction is recorded, Lo is even sample data of the left audio channel, R1 is odd data of the right audio channel, and even data of the right channel, L , is the area where left channel odd data is recorded, and in standard mode, 2 tracks y! - It is divided into 4 and distributed by the R channel and even and odd samples. On the other hand, in LP mode, the data is distributed in the first half, second half, even number, and odd number samples, and LRo in (2) in the same figure is the even numbered sample data in the first half of the left and right channels, LR; is the odd numbered data in the second half of the left and right channels, and LRo is the odd numbered data in the second half of the left and right channels. The even-numbered sample data LR1 in the second half of the left and right channels is an area for recording the odd-numbered data in the first half of the left and right channels. Figure 12 shows an RA with valley filtering for two tracks of PCM data to realize DAT interleaving.
This is an example of an M map. The vertical axis is the upper address of RAM, and the horizontal axis is the lower address. Also, Bo, B,・
...B12. is the storage area for block-based data on track A, bOnbK...bit? is an area that stores data in units of 10 blocks on the B track. The C2 code for error correction is generated by 32 data from lower addresses 00 to 1F, and the C1 code is a vertical address that stores data in units of 2 blocks and every other block. It consists of 32 pieces. Table 2 shows the order and addresses for loading AD-converted data into the RAM or loading data to be DA-converted from the RAM in the standard mode.

As shown in Figure 7, slots 1 and 2 in the table correspond to the process of accessing the RAM f by dividing the upper and lower 8 bits of one sample of 13-bit data into two parts. As a result, the standard mode interly-1 shown in FIG. 11 is realized.

In this RAM map, in the present invention, in the LP mode, addresses are created in each of the first and second halves in the order shown in Tables 3 and 4, and the RAM is accessed. The data and address to be accessed are determined by the data conversion circuit described above,
It is designed to correspond to an inverse conversion circuit.

The following margins are Table 2, Table 5, and Table 4. Also, the first half and second half of the RAM address are made in a symmetrical format in which the upper 1 bit of the RAM address is inverted. As a result, the 11th
The LP mode array conversion and interleaving shown in FIG. 2 can be realized.

The thirteenth factor is an embodiment of a RAM address generation circuit which is used for both the m-leaf mode and the LP mode interleave according to the present invention.

The same signal names shown in FIGS. 3 to 9 in the figure are signals with the same content as described above, 11 is a RAM address bus, 12 is a RAM address bus, and 12 is a RAM address bus.
is a divide-by-2 counter, 13 is a divide-by-4 counter, 14 is a divide-by-4 counter, and 14 is a divide-by-4 counter.
Frequency division counter, 15 is 5/2 frequency division counter, 13 is 71
[1 circuit, 17 and 15 are switch for selection of A and No. (B)
19 is an exclusive OR circuit, 20 is a concatenated sum circuit, 11
~! , are signal input terminals, and the input terminal 4 identifies the slot 1.2 mentioned above with l L I mh a 13
No. UL5 manual power, input terminal 4. inputs a switching signal that identifies LP mode and standard mode with 1H'' and ``L'', inputs the reset number and frame zg'@ shown in Figures 3 and 4 to input terminals IO and I, and inputs the input terminals IO and I. 11° is the yth
a, input the timing 1 and timing 2 times numbers shown in Fig. q.

Here, the switching circuit 17 for selecting the f6 signal selects the timing 1 signal in the standard mode and the timing 2 signal in the LP mode, and the switching circuit N18 for signal selection selects the 4 frequency divider counter 15 in the quasi-standard mode. select the lower bit A' output of
In LP mode, frame 1 signal is selected. In addition, the carry power number 1d of the frequency divider counter 15 by 4 is controlled by the quotient reserve circuit 20, and in the Lp mode, the lower bit operates in the same way as the frequency divider by 2 counter 12 (A=A'). , standard mode, and LP mode.In the early image mode, counters 12 to 15 are reset to the 2-track motherboard where the cylinder rotates once, and in the %LP mode, the boundary dividing the second half of MiJ (cylinder 1/2
Reset the counter every time (rotation). Therefore L.P.
In the mode, the target address 4'tr is obtained by inverting only the upper bits of the address by one frame number.

As a result of the above, the RAM addresses generated in standard mode and Lp mode are as shown in Table 5, and are shown in Tables 3 to 5 (Table 5 does not show the RAM address number 100). Realize the address signal.

Table 5 [Effects of the Invention] According to the present invention, an LP mode data conversion processing circuit can be inserted as an external circuit between the digital signal processing circuit and the RAM. In addition, the flag processing circuit allows for the same operation as in the conventional interpolation circuit or in LP mode.
RAM address generation that realizes Lp mode interleaving! , the L of the digital signal processing circuit for the conventional standard mode, such as the circuit can be used both for the S quasi mode and easily configured.
There is a young fruit in which the LP-compatible circuit for P-compatible is simple and the LP mode can be easily realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a PCM signal recording and reproducing apparatus as an embodiment of the present invention. 4 to 4 are timing diagrams showing the operation of the pCM@- number recording and reproducing apparatus of the present invention, FIG. 5 is a circuit diagram showing the configuration of a data conversion circuit in an embodiment of the present invention, and FIG. A circuit diagram showing the configuration of an array conversion circuit in an embodiment of the present invention, FIG. 7 is a timing diagram showing the array conversion operation, and FIG. 8 is a circuit diagram showing the configuration of an array inversion circuit in an embodiment of the present invention. ,
FIG. 9 is a timing diagram showing the array inversion operation, FIG. 10 is a circuit diagram showing the configuration of a flag processing circuit in an embodiment of the present invention, and FIG. 11 is a signal diagram showing the interleave format of standard mode and LP mode. , FIG. 12 is an I(AM map) diagram for realizing interleaving of the address circuit in one embodiment of the present invention, and FIG. 15 is a circuit diagram showing the configuration of the address circuit in one embodiment of the present invention. ...Digital signal processing circuit 2...Data conversion circuit 21 River compression circuit 22...
Array conversion circuit 23... Arrangement inversion circuit 24...
- Decompression circuit 25...Flag processing circuit 26
, 27... Output control buffer circuit 255.24M...
・Flag decoding circuit representative Patent attorney Uo Ogawa

Claims (1)

[Claims] 1. A magnetic head is attached to a rotating cylinder, and a magnetic recording medium wound around the cylinder is caused to run, and the process is completed each time one magnetic head scans the magnetic recording medium once. PCM signals are recorded and reproduced on the magnetic recording medium track by track using the signal obtained as a track signal, and at the time of recording, the signal to be recorded is input/output to a storage circuit to generate an error correction code and perform interleaving. In a PCM signal recording and reproducing apparatus equipped with a signal processing circuit that performs error correction and deinterleaving processing by inputting and outputting data to and from the storage circuit during reproduction, a delay circuit (22) that delays and outputs at least an input data signal is provided. , 23) and a selection circuit (26, 27) for selecting an output data signal of the delay circuit is connected between the signal processing circuit and the storage circuit, and the data conversion circuit A first operation mode in which the data signal passing through this is converted into non-time series data corresponding to a predetermined interleaving during recording, and the reverse conversion is performed during playback, and a first operation mode in which the data signal passing through this is not converted at all during recording. The second signal is passed through without any conversion, and is passed through without any conversion during playback.
A PCM signal recording/reproducing device characterized in that the following operation modes can be selectively adopted by a command. 2. In the PCM signal recording and reproducing apparatus according to claim 1, the data conversion circuit in the first operation mode converts time series data An and Bn in units of 12 bits into the upper side in two channels where n is a natural number. PCM with 8 bits as a unit
Divide into data Anu, Bnu and PCM data Anl, Bnl in which the lower 4 bits are the unit, and place Anl in the upper part and Bnl in the lower part, and PCM data in 8 bits as a unit.
In addition to composing the CM data ABnl, time series PCM data A_4n, B_4n, A_4n+1, B_4n+1, A in 12-bit units
_4n+2, B_4n+2, A_4n+3, B_4n+
3 in 8-bit units, non-time series PCM data A_4n
u, AB_4nl, A_(_4_n_+_1_)u, A
B_(_4_n_+_1_)l, B_4nu, A_(_
4_n_+_2_)u, B_(_4_n_+_3_)u
, AB_(_4_n_+_2_)l, B_(_4_n_
+_2_)u, AB_(_4_n_+_3_)l, B_
(_4_n_+_3_)u, or convert the PCM data into a non-time series array in 8-bit units to the above 1.
A PCM signal recording and reproducing device comprising a conversion circuit that operates to convert into time-series PCM data in 2-bit units. 3. A magnetic head is attached to a rotating cylinder, and the magnetic recording medium wound around the cylinder is made to run at a speed V, so that the magnetic recording medium is completed every time one magnetic head scans the magnetic recording medium once. The signal is a track signal, and two-channel PCM signals that are input during a predetermined time required for the magnetic recording medium to travel two tracks are divided into an even-numbered signal and an odd-numbered signal in the input order.
A first operation mode in which the channels or even numbers and odd numbers are arranged and recorded differently in the first half or the second half of the track, and a magnetic recording medium is run at a speed of V/2, and the magnetic recording medium is recorded on the two tracks. 2-channel PC that inputs the first and second half of the predetermined time required to travel for minutes
A PCM signal that can adopt a second operation mode in which the M signal is divided and the PCM signals input to the first half and the second half are arranged and recorded in the first half or the second half of two adjacent tracks so as to be different from each other. The recording/reproducing device includes a memory circuit (3) for storing the PCM signal and an address circuit for generating a memory address of the memory circuit (3),
The address circuit switches from the first counter (12) to the second counter (13) in response to a first counter (12), a second counter (13), and an operation mode switching command (15). A control circuit (2) that controls the output carry
0) and the operation mode switching command (15), the output (A') of the second counter (13) or another signal (12
), and the output of the switching circuit (18) causes the first counter (12) to
an inverting circuit (19) for inverting or not inverting the output (A) of the counter, and using the output of each of the counters as a signal constituting an address. Recording and playback device. 4. A correction circuit that adds an error correction code to the PCM signal to be recorded and corrects errors in units of n bits during playback, divides the n-bit data corrected by the correction circuit into multiple pieces, and performs correction. In a PCM signal reproducing device comprising a data conversion circuit (2) that combines one or more pieces of other processed m-bit data to form one piece of data, the correction circuit is the result of correction processing, Information representing data reliability and corrected data on a one-to-one basis
The information is output as flag data, and flag data representing the least reliable information among the plurality of pieces of flag data corresponding to the data output from the data conversion circuit (2) is output as one flag data. A flag processing circuit (25) is provided to select and output the data conversion circuit (25).
1.) A PCM signal recording and reproducing device characterized in that data outputted by the flag processing circuit (25) and flag data outputted by the flag processing circuit (25) are arranged in a one-to-one correspondence.