JPH03136155A - Memory sharing control system - Google Patents

Abstract

PURPOSE:To reduce the area of an LSI chip constituting a register and to miniaturize it by using one auxiliary register as a storage register of parameters different from one another. CONSTITUTION:Auxiliary transfer counter (TCRS) parts of a transfer block pointer (TBC) 33 and a transfer counter (TCR) 19 can be shared among registers of transfer quantity elements, and the SPRS 16 part of a transfer parameter pointer (TPP) can be shared among registers of transfer direction elements. Thus, the number of registers is reduced to economize the memory area, and a memory sharing control system which increases the data transfer processing speed is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory sharing control method when an information processing apparatus includes a CPU and directly transfers data between a memory and an input/output device.

[Prior art] Figure 3 is a DM explaining a conventional method of using memory areas.
It is a memory map diagram in the A control device, and in the same figure,
2 is a RAM as a memory connected to the CPU, 3 is an input/output device (hereinafter referred to as ■/○), 4.5 is an address and data bus, and 7 is a DMA control device.

The DMA control device 7 includes an access control section 8° latch 9
．． Work memory 11. Transfer parameter pointer 12. A transfer block counter 13 is provided. 14 is a transfer parameter memory, which is set in an arbitrary external memory space. The work memory 11 is a source pointer (hereinafter referred to as SP
R) 15, Reserve source pointer (hereinafter referred to as 5PR8
)16. Destination pointer (hereinafter referred to as
DPR)17. Reserve destination pointer (hereinafter referred to as DPRS)18. Transfer counter (hereinafter referred to as TCR)19. Preliminary transfer counter (hereinafter referred to as TC)
R8) 20 and an increment/decrement counter (hereinafter referred to as ■/D) 21. Data blocks 23 and 24 are stored in the transfer parameter memory 14.
．． 25 etc. are provided. A buffer gate 22 is provided between the buses 4 and 5 and the work memory 11, latch 9, etc. FIG. 4 is a block diagram showing the memory map of FIG. 3.

Next, the operation of performing DMA transfer between the input/output device (hereinafter referred to as Ilo) 3 and the RAM 2 will be explained. First, simple transfer will be explained. In single transfer, the DMA transfer ends when a preset number of transfer bytes (words) have been transferred. Enter the first address of the data block you want to transfer from the transfer source (l103 or RAM2) in 5PR15 and S.
Write to PR316. Furthermore, the transfer destination (RAM2 or l1
03) The first address of the memory block is written to the DSP 17 and DSPS 18. And TCR19 and TC
Write the number of bytes (words) scheduled to be transferred to R320.

Next, the access control unit 8 transfers bus usage rights to the DMA control device (
Transfer starts when set to 7 (hereinafter referred to as DMAC).

First, the read address in 5PR15 is output to the address bus 4. This output enters the I/D 21, is incremented by +1 or -1, and is updated and recorded again with the increased or decreased value to 5PRI5. Next, the data read from RAM2 or l103 is temporarily stored in data latch 9.

In the next cycle, the address for writing in DPRI 7 is output to address bus 4. Then, the data in the data latch 9 is output onto the data bus 5, and the data is transferred to l10.
3 or written into RAM2. Thereafter, the above-described operations are repeated to continue the DMA transfer. The value of TCR19 is I/
Each time D21 is incremented by +1, it is incremented by -1, and the value subtracted from TCR19 is updated and recorded again. Since the contents of TCR19 decrease with each transfer, when the value of TCR19 reaches LLOIT, access control unit 8 returns the right to use bus 4.5 to the CPU and ends the data transfer.

Next, repeat transfer will be explained. Repeated transfer simply repeats a single transfer.

Since the first address of the transfer source is 5PR316, the first address of the transfer destination is DPR31B, and the number of transfer bytes is also recorded in TCR820, the above-mentioned 3 4 SPR15, DPRI7. 5PR instead of TCR19
816, DPR318, and TCR820 to perform data transfer in the same manner.

Next, array chain transfer will be explained.

This transfer involves time-divisionally transferring multiple data blocks using one channel. In this case, the transfer parameter memory 14 is also used. The transfer parameter memory 14 is arranged in a memory space outside the DMAC 7. FIG. 3 shows the case of transfer of three data blocks. The first data block 23 contains the starting address of the transfer source.

The transfer destination start address Δ△Δ and the number of transfer bytes m are stored in the second data block 24, the transfer source start address XIXI, the transfer destination start address Δ1Δ1 . Similarly, the number n of transferred bytes is stored in the third data block 25 as X2X2. Δ2Δ2. J! are written in advance in order. The number of data blocks is not limited to three and can be set freely. Before starting the transfer, write the start address (αα) of the transfer parameter memory to the transfer parameter pointer (hereinafter referred to as TPP) 12 in the DMAC 7, and write the number of data blocks 113 N to be transferred to the DMAC 7.
Transfer block counter (hereinafter referred to as TBC) 13 in
write to.

Next, when the transfer starts, the address bus 4 has TPP12.
Outputs the address of the transfer parameter memory 14 from
Δ and m to TCR19° and TCR320. After this operation, T P P ]-2 becomes the start address (ββ) of the transfer parameter of the second data block 24, and the TBC 13 is decremented by one, so that the number of remaining blocks is 112 IT. The next operation is similar to the single transfer described above. The content of TCR19 is 1'01
', the TPP 12 outputs the address again.

The value 1'3'' of the TBC13 is decremented by 1 each time the contents of each data block 23, 24, and 25 are transferred as described above.When the number of remaining transfer blocks reaches ``OIT'', the transfer ends.

Next, link array chain transfer will be explained. Unlike array chain transfer, the transfer method does not require the transfer parameters of data blocks 23 to 25 to be arranged in order. Instead, the starting address (XXX) of the transfer source is used as a transfer parameter.

XIXI, X2X2) 1 Transfer destination start address (△△△, △
1△1. Δ2Δ2) In addition to the transfer byte numbers m, n, and jQ, the addresses αα, ββ, and γγ where the transfer parameters of the next transfer block are located are required.

First, the transfer parameters are written in the transfer parameter memory 14. Before starting the transfer, the starting address (αα) of the transfer parameter memory is written into the TPP 12. There is no need to write the data block number to TBC13.

Next, when the transfer starts, the address bus 4 has TPP12.
outputs the address of the transfer parameter of the first data block 23 from DPRl7. △Δ△ to DPR318
, TCR19.

Transfer m to TCR520. Then, the address of the transfer parameter of the next block is written to the TPP 12. When this operation is completed, the TPP 12 indicates the starting address of the next transfer parameter. Next are 5PR15, DPRl, 7. which were transferred in the same way as the single track. Transfer is performed based on the data of TCR19.

When the contents of TCRl9 become 0'', the address containing the parameters of the second data block 24 is output from the TPP12 to the address bus 4 again, and
PRl7. DPR818°TCR19. At the same time as writing TCR820, write the address of the next transfer parameter to TPP12.
Move to.

When the address written to the TPP 12 is 10'', the transfer ends.

However, as shown in FIG. 4, the register of the transfer quantity element is TB.
C13, TCRl9. It consists of a TCR 320 and a decrement counter 21, and the transfer address register is 5PR1.
5,5PR316,DSP17,DSPS18. Array address pointer (equivalent to transfer parameter pointer 12)
12a.

[Problems to be Solved by the Invention] However, in the conventional memory use control method, many memory areas and registers are used to set parameters necessary for data transfer, and the access control unit 8 uses these memory areas and registers. The disadvantage is that it takes time to process because it has to be accessed each time.

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a memory sharing control method that reduces the number of registers, saves memory area, and speeds up data transfer processing.

[Means for Solving the Problems] The present invention is a method for controlling memory use in an information processing device consisting of a CPU, a main memory, and a DMA control device, in which parameters necessary from the start to the end of data transfer are controlled. When a storage register and a spare register exist, a spare register for one parameter is shared as a storage register for different parameters.

[Function] Parameters are stored twice in the spare register for simple repeat transfer, but since the registers and parameter generation points provided for the transfer logic and array chain transfer logic are secured, the memory map can be saved. In the overall structure, there are parts of the registers that can be shared, and registers can be shared as much as possible to save memory space and transfer time.

[Example] The present invention will be explained below with reference to the drawings.

FIG. 1 shows a DM in which the memory sharing control method of the present invention is implemented.
It is a memory map diagram in the A control device, and in the same figure,
2 is the main memory RAM of the CPU, 3 is the input/output device,
4 and 5 are address and data buses, and 37 is a DMA control device.

The DMA control device (DMAC) 37 includes an access control unit 8
．． Latch9. It is equipped with a work memory 11. 14 is a transfer parameter memory, which is set in an arbitrary external memory space. The work memory 11 contains a source pointer (
SPR)15. Transfer 9- 10- Parameter pointer (TPP) 32. Destination pointer (DPR)17. Reserve destination pointer (DPR8)18. Transfer counter (TCR)
19. It includes a transfer block pointer (TBC) 33 and an increment/decrement counter (I/D) 21. The transfer parameter memory 14 is provided with data blocks 23, 24, 25, etc., and destination areas 27, 24, 25, etc.
A reserve destination area 28 is provided. Work memory 1
Each parameter of the data block at the destination address indicated by the destination area 27 is temporarily stored in the TPP 32 in the TPP 1 . T
The number of data blocks scheduled to be transferred is stored in BC32.

Since the data transfer operation is the same as the conventional one, the explanation will be omitted and only the sharing of memory and registers will be explained.

In the case of a single track, even after the -th data transfer is completed, the first address of the transfer source is stored in the 5PR15, and the first address of the transfer destination is stored in the DPR17 at the time of startup and held. In the case of array chain transfer or link array chain transfer, everything below the starting address of the transfer source is transferred from each data block 23 to 25 of the transfer parameter memory 14, so even if there is no spare source pointer 5PR816, the starting address can be secured. Further, since the number of bytes (words) scheduled to be transferred in the TCR 19 can be obtained from each data block 23 to 25, data transfer can be performed accurately.

FIG. 2 shows a summary diagram of FIG. 1. In the transfer quantity register, the preliminary transfer counter (TC
R8) portions can be shared. In addition, in the transfer direction element register, a spare source pointer (SP
R3) portions can be shared.

In this way, single transfer, repeat transfer, array chain transfer, and link array chain transfer can be realized with a small amount of logic.

Note that the present invention is not limited to DMA devices, and can also be applied to sharing in general memory use.

[Effects of the Invention] 11-12- As explained above, according to the present invention, there is provided a method for controlling memory use in an information processing device including a CPU, a main memory, and a DMA control device. When there are registers and spare registers that store parameters required until the end, the spare register for one parameter is shared as a storage register for a different parameter, so the LSI chip of the hardware that makes up the register It becomes possible to reduce the area and downsize.

Furthermore, data transfer time and memory area can be saved in DMA transfer, and information processing ability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a memory map of the memory sharing control method of the present invention.
2 is a summary diagram of FIG. 1, FIG. 3 is a conventional memory map diagram, and FIG. 4 is a summary diagram of FIG. 3. 2... RAM, 3... Input/output device, 4, 5... Bus, 8... Access control section, 9... Data latch,
11...Work memory, 14...Transfer parameter memory, 15...Source pointer (SPR), 16...
- Spare source pointer (SPR8), 17... Destination pointer (DPR), 18... Spare destination pointer (DPR8), 19...
Transfer counter (TCR), 20...Preliminary transfer counter (TCR8), 21...Increment/decrement counter (I/D), 23-25...Data block, 12.32...Transfer parameter pointer ( T
PP), 13.33...transfer block counter (TB
C), 37...DMA control device (DMAC).

Claims (1)

[Claims] A control method for memory use in an information processing device consisting of a CPU, main memory, and DMA control device, in which there are registers and spare registers that store parameters necessary from the start to the end of data transfer. A memory sharing control method characterized in that a spare register for parameters is shared as a storage register for different parameters.