JPH03136251A - Pn junction type field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a PN junction type field effect transistor which is lower than a conventional one in parasitic capacity and prevented from deteriorating in high frequency characteristics without increasing in parasitic resistance by a method wherein a first layer of first conductivity type, a second high concentration layer of first conductivity type formed on both the side of the first layer respectively, a second conductivity layer formed on the first layer of first conductivity type, and the like are provided. CONSTITUTION:A field effect transistor of this design is composed of the following: a first layer 3 of first conductivity type formed on a semiconductor substrate 1; second layers 4 of first conductivity type which are higher than the first layer 3 in impurity concentration and formed on both the sides of the first layer 3: a second conductivity type 7 formed on the first layer 3 of first conductivity type on the semiconductor substrate 1; a source electrode 9 and a drain electrode 10 formed on the second layers 4 of first conductivity type respectively; and a gate electrode 11 formed on the second conductivity type layer 7. For instance, as shown in a figure, the n-type layer 3, the n<+>-type layers 4, and the p<+>-type layer 7 are formed on the semi-insulating GaAs substrate 1. An SiO2 film 5, the source electrode 9 and the drain electrode 10 of AuGe/Ni, and the gate electrode 11 of Al/Ti or the like are formed on the above the layers.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a pn junction field effect transistor and a method for manufacturing the same.

(b) Conventional technology Pn junction field effect transistors have advantages over Schottky contact field effect transistors, such as higher gate breakdown voltage and larger logic amplitude. Suitable for \ applications.

FIGS. 3(a) to 3(e) are process explanatory diagrams for explaining a conventional method of manufacturing a pn junction field effect transistor.

First, using a resist (32) formed on a semi-insulating GaAs substrate (semiconductor substrate) (31) as a mask, Si ions are implanted into the substrate (31) to form an n-type layer (33).
(Fig. 3(a)).

After removing the resist l-(32), a resist (32°) is newly formed on the semi-insulating GaAs substrate (31), and Si ions are implanted using the resist (32°) as a mask to form an n + type A layer (34) is formed (FIG. 3(b)).

After removing the resist (32'), an insulator (35) is formed on the entire surface of the substrate (31), an opening (36) is formed in the insulator (35), and then Zn is formed using the insulator (35) as a mask. ion implantation (or Zn diffusion) to form a p4 type layer (3
7) (Fig. 3(C)).

An n-type layer (33), an n"-type layer (34), and a p'"-type layer (
After performing heat treatment to activate the ohmic electrode (37), a resist is formed on the area other than the area where the ohmic electrode is to be formed, an ohmic polar metal is formed on the entire surface, and the resist is removed and heat treated to form the ohmic electrode (38). (38J is formed (Fig. 3(d)).

A resist is formed in areas other than the area where the gate electrode is to be formed, a gate electrode metal is formed on the entire surface, and the resist is removed to form a gate electrode (39) (FIG. 3(e)).

(c) Problems to be Solved by the Invention In a pn junction field effect transistor completed by a manufacturing method such as a double series, the p4 type layer (37) is replaced by the n type layer (33).
Because it has a structure embedded in the p′″ type layer (3
7) Pn junctions are formed on both sides.

The capacitance generated by this pn junction becomes a parasitic capacitance, resulting in deterioration of the high frequency characteristics of the transistor and a reduction in the suctioning speed.

In addition, when the p4 type layer (37) is formed by diffusion, in this diffusion step, or when the p4 type layer (37) is formed by ion implantation, in the activation treatment after this ion implantation step, The 11th layer (37) is larger than the width of the opening (36) in the insulator (35), that is, the effective gate length becomes larger, leading to deterioration of the high frequency characteristics of the transistor.

Furthermore, since the n'' layer (34) is not formed in a self-aligned manner with respect to the gate electrode (39), the gap between the n+ layer (34) and the gate electrode (39) becomes large, which occurs between the source and gate electrodes. There is a risk that parasitic resistance will increase, leading to deterioration of the high frequency characteristics of the transistor.

(d) Means for Solving the Problems The present invention provides a first conductivity type layer formed on a semiconductor substrate, and a first conductivity type layer formed on both sides of the first first conductivity type layer of the semiconductor substrate. The second layer of high i seismic intensity from the first conductivity type layer of 1
a first conductivity type layer formed on the first conductivity type layer of the semiconductor substrate; a second conductivity type layer formed on the first conductivity type layer of the semiconductor substrate;
This is a pn junction field effect transistor comprising a source electrode and a drain electrode formed on a conductive type layer, and a gate electrode formed on the second conductive type layer.

In addition, the present invention includes a step of implanting ions into a semiconductor substrate to form a first layer of the first conductivity type, and etching the gate of the first layer of the first conductivity type at a portion other than a portion where a pole is to be formed to form a convex portion. a step of implanting ions into the recess to form a second first conductivity type 1 layer with a higher (seismic intensity) than the first 141 type layer; and a step of implanting ions into the projection. A pn characterized by comprising the steps of forming a second conductivity type layer by implanting, forming a source electrode and a drain electrode on the concave portion, and forming a gate electrode on the convex portion. This is a method for manufacturing a junction field effect transistor.

(E) Effect According to the present invention, the area where the second conductivity type layer contacts the first first conductivity type layer and the second first conductivity type layer can be significantly reduced.

Furthermore, since the second conductivity type layer is formed on the convex portion, the second conductivity type layer does not expand in a subsequent process.

Furthermore, since the convex portion and the four portions are continuous, the second first conductivity type layer is formed in a self-aligned manner with respect to the gate electrode.

(f) Embodiment FIGS. 1(a) to 1(i) are process diagrams for explaining a method of manufacturing a pn junction field effect transistor according to an embodiment of the present invention.

First, using a resist (2) formed on a semi-insulating GaAs substrate (semiconductor substrate) (1) as a mask,
) to form an n-type layer (first conductivity type layer) (3) (FIG. 1(a)). Note that the implantation conditions at this time are implantation energy of 100 KeV and implantation amount of I.sub.X I.sub.Q "cm.sup.-".

After removing the resist (2), a new semi-insulating GaAs substrate (
1) Forming a resist (2°) on top (Fig. 1(b))
Using the resist (2゛) as a mask, the substrate (1) is exposed to C.
Etching is performed using Cl t F t or active ion etching to form recesses (a) and projections (b) (FIG. 1(C)). This convex portion (b) becomes a portion where a gate electrode is to be formed.

S is applied to the substrate (1) using the resist (2°) as a mask.
Ion implantation is performed to form an n" type layer (second first conductivity type layer) (4) (FIG. 1(d)).

The implantation conditions at this time are implantation energy of 150Ke~
I, the injection amount is 5 x 10 "Cm-""C.

5 by ECR plasma CVD method or vacuum evaporation on the entire surface.
2000 people form 101 membranes (5) (Figure 1 (e))
.

By removing the resist (2°), the resist (
2°), remove the Sin film (5), form a new resist (6), and remove the resist (6) and the remaining S film (5).
Using the iO* film (5) as a mask, Zn ions are implanted to form a p+ type layer (second conductivity type layer) (7) (first
Figure (f)). The implantation conditions at this time were an implantation energy of 15 KeV and an implantation amount of 5.times.10"cm.sup.-".

After removing the resist (6), apply ECR plasma C~'D to the entire surface.
700 SiN films (8) were formed by the method, and heat treatment was performed using the SiN films (8) as a protective film to form an n-type layer (3),
Activate the n'' type layer (4) and the p1 type layer (7) (
Figure 1(g)). Note that the heat treatment may be performed in an arsine (AsHl) atmosphere without forming the SiN film.

After removing the SiN film (8), a source electrode (9) and a drain electrode (10) made of AuGe/Ni are formed (FIG. 1(h)).

Finally, the gate consisting of A l / T i etc. is connected to the pole (11
), a pn junction field effect transistor according to an embodiment of the present invention is completed (FIG. 1(i)).

Further, FIGS. 2(a) to 2(d) are process explanatory diagrams for explaining other embodiments of the present invention, and the state in FIG. 2(a) corresponds to the state in FIG. 1(f>). The process up to this point is the first step.
Since it is the same as that explained in the figure, the explanation will be given starting from FIG. 2(b).

A WSi film (12) is formed on the entire surface by sputtering, and heat treatment is performed using the WSi film (12) as a protective film to form an n-type layer (3), an n4-type layer (4), and a p4-type layer (7).
(Fig. 2(b)). In addition, WSi film (12
) is a heat-resistant date metal material, so the WS after heat treatment
1 film (12) can be used as a gate electrode.

~Selectively remove the VSi film (12) and remove the gate electrode (1
3) (Fig. 2(C)).

Finally, by forming a source electrode (14) and a drain electrode (15), a pn junction field effect transistor of another embodiment of the present invention is completed (Fig. 2(d)) In this embodiment, the heat treatment described above is performed. Compared to the embodiment in which the SiN film (8) is used as the protective film, the step of forming the 5iN film (8) can be omitted.

In the above embodiment, the first and second first conductivity type layers are n
Although the type and second conductivity type layer are p type, the first and second first conductivity type layers may be p type and the second conductivity type layer may be n type.

Furthermore, in the above-described embodiments, the second conductivity type layer is formed using ion implantation, but it may also be formed by diffusion.

(G) Effects of the Invention According to the present invention, it is possible to reduce the area where both side surfaces of the second conductivity type layer are in contact with the first first conductivity type layer and the second first conductivity type layer, compared to the conventional method. can reduce parasitic capacitance. Furthermore, since the second conductivity type layer does not expand in subsequent steps, deterioration of high frequency characteristics can be prevented. In general, since the second first conductivity type layer is formed in a self-aligned manner with respect to the gate electrode, deterioration of high frequency characteristics due to an increase in parasitic resistance between the source and gate electrodes can be prevented.

[Brief explanation of the drawing]

Figures 1 (a) to (i) and Figures 2 (a) to ((1)
is a process explanatory diagram for explaining the method of the present invention, FIG.
) to (e) are process explanatory diagrams for explaining the prior art. (1)...semi-insulating GaAs substrate, (3)...n type layer, (1)...n+ type layer, (7)...p+ type layer, (9
)(14)...source electrode, (10)(15)...
Drain electrode, (11) (13)...gate electrode, (a
)...Concave portion, (b)・Convex portion.

Claims (1)

[Scope of Claims] 1. A first first conductivity type layer formed on a semiconductor substrate, and the first first conductivity type layer formed on both sides of the first first conductivity type layer of the semiconductor substrate. The second layer has a higher concentration than the first layer.
a conductivity type layer, a second conductivity type layer formed on the first first conductivity type layer of the semiconductor substrate, and a source electrode and a drain electrode formed on the second first conductivity type layer. , and a gate electrode formed on the second conductivity type layer.
Junction field effect transistor. 2. A step of implanting ions into the semiconductor substrate to form a first first conductivity type layer, and etching a portion of the first first conductivity type layer other than the portion where the gate electrode is to be formed to form convex portions and concave portions. a step of implanting ions into the concave portion to form a second first conductivity type layer having a higher concentration than the first first conductivity type layer; A pn junction field effect characterized by comprising the steps of forming a biconductivity type layer, forming a source electrode and a drain electrode on the concave portion, and forming a gate electrode on the convex portion. Method of manufacturing transistors.