JPH0314111A - Microprocessor power save controller - Google Patents

Abstract

PURPOSE:To sufficiently execute the power save by executing the power save by delaying a system clock when a microprocessor is executing a halt instruction, and returning the system clock to a period before executing the halt instruction, in case the halt instruction is released by an interruption controller. CONSTITUTION:A state discriminating device 10 supervises the state of a microprocessor 1, and outputs its state. A system clock varying device 5 varies a frequency by the state of the microprocessor 1, and outputs a system clock 9 as a frequency corresponding to the state to the microprocessor 1. Subsequently, in case the microprocessor executes an access to a storage device 2 and a peripheral equipment 3, the access can be executed by the maximum operating frequency by the system clock varying device 5, and on the other hand, in case a job to be processed does not exist, the system clock is delayed in accordance with necessity. In such a way, the power save effect can be displayed enough without decreasing a processing speed of the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Field of Application The present invention is a microcomputer used in office automation equipment such as battery-powered word processors and personal computers.
TECHNICAL FIELD The present invention relates to a power saving control device for a processor.

BACKGROUND OF THE INVENTION Conventionally, microprocessor controllers of this type include storage devices and peripheral devices connected to the system bus signals of the microprocessor, and interrupt controllers and system clocks to prompt the restart of the microprocessor.・When there is no job to be processed by the microprocessor, the microprocessor is equipped with a generator, etc. for the purpose of power saving.
) was realized by executing the command.

FIG. 4 shows the configuration of a conventional microprocessor control device.

In FIG. 4, 21 is a microprocessor, 22 is a storage device, 23 is a peripheral device, 24 is an interrupt control device,
25 is a system clock generator.

26 is a system bus created by the microprocessor 21, and 22-25 are directly connected to 26.

24, an interrupt is generated by the peripheral device 23, and IRo~
When any of the IRs 7 becomes active, an interrupt request 27 to the microprocessor 21 becomes active.

Next, the operation of the above conventional example will be explained.

In FIG. 4, devices 21 to 25 generally have a 0MO8 structure for the purpose of reducing power consumption.

As is well known, the power consumption of a device with an 0MO3 structure increases in direct proportion to its operating frequency. (FIG. 3) 21 is a microprocessor operating in synchronization with the system clock as shown in FIG. Output. The storage device 22 starts operating by the signal 28, and the access time tacc
After this period has elapsed, the data is output to the system bus.

Normally, in order to process a job, memory fetching and instruction execution are continuous, and the microprocessor 21 operates at the maximum processing speed and consumes maximum power.

When there are no more jobs to be processed (such as when waiting for key personnel), a halt command is generally executed.

At time H in FIG. 6, the microprocessor 21 executes the halt instruction, and after that, only a part of the internal circuit of the microprocessor 21 is operating, and the power consumption is the minimum and power saving is possible. It becomes possible.

When a job to be processed occurs (such as by key manual input), when any of the interrupts 31 (IRQ to IRE>) of the interrupt control device 24 becomes active, the interrupt request 2 becomes active, and at time S in FIG. Now, the microprocessor starts processing the job again and frees up memory.
Fetching and instruction execution occur continuously, and power consumption is maximized.

In this way, the power saving effect can be obtained by simply executing the halt command by using a 0MO8 structure as the conventional micro processor 5beno.

Problems to be Solved by the Invention However, in the conventional microprocessor power saving system described above, the frequency of the system clock generator 26 is generally fixed, and the operating frequency is not increased in order to prioritize processing speed. If you use it at maximum, the power saving effect is not sufficient, and if you use it at -1, slowing down the system clock of the micro processor to get sufficient power saving effect, there is a problem that the job processing speed will slow down. Ta.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent power saving control device for a microprocessor that can fully exhibit the power saving effect without reducing the processing speed of the microprocessor.

Means for Solving the Problems Page 6 In order to solve the above object, the present invention varies the storage device and peripheral devices connected to the system bus signal of the micro-70 processor and the system clock of the microprocessor. a system clock variable device for determining the operating state of the microprocessor, a state determining device for determining the operating state of the microprocessor, and an interrupt control device for prompting restart of the microprocessor; When the system clock is slowed down to save the power of the micro-70 setter and the halt instruction of the microprocessor is released by the interrupt control device, the system clock is returned to the cycle before executing the horn 1 instruction. This enables high-speed operation.

Therefore, according to the present invention, when the microprocessor accesses the storage device and peripheral devices, the system clock variable device allows the access to be made at the maximum operating frequency, without reducing the processing speed. do not have. Furthermore, when there are no jobs to be processed, the power consumption of the microprocessor can be reduced by delaying the instant clock as necessary.

Example FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 1 is a microprocessor, and a storage device 2, a peripheral device 3, and an interrupt control device 4 are connected to a system bus 6 created by the microprocessor.

The status determination device 10 is directly connected to the microprocessor 1, monitors the status of the microprocessor 1, and instructs the system clock variable device 5 to determine the status of the microprocessor 1.
Outputs the status of.

The system clock variable device 5 varies the frequency depending on the state of the microprocessor 1, and outputs the system clock 9 to the microprocessor 1 at a frequency corresponding to the state.

Next, the operation of the above embodiment will be explained.

In FIG. 1, microprocessor 1 is a microprocessor that operates in synchronization with the system clock as shown in FIG. A storage device read signal 8 is output.

The storage device 2 starts operating in response to the storage device read signal 8, and outputs data to the system bus after the access time tacc has elapsed.

At this time, the status determination device determines that the system is in the run state, and outputs the fact that it is in the run state to the system clock variable device 5. Accordingly, the system clock variable device 5 outputs the system clock at the maximum operating frequency to the microprocessor 1.

Normally, in order to process a job, memory fetching and instruction execution are continuous, and the microprocessor 1 operates at maximum processing speed and consumes maximum power.

When there are no more jobs to be processed (such as when waiting for key personnel), the 71/l- command is generally executed.

At this time, the state determining device determines that the system is in the H/V) state and outputs to the system clock variable device 5 that it is in the halt state. As a result, the system clock variable device 5 outputs a system clock whose frequency has been lowered to the microprocessor 1.

At time H in Figure 2, microprocessor 1 executes the halt instruction, and only part of the internal circuit of microprocessor 1 is operating at a low frequency, so the power consumption is just that of executing the halt instruction. It is also smaller than the previous model, allowing for sufficient power savings.

When a job to be processed occurs (such as key manual input), any of the interrupts 11 (IRO to IR7) of the interrupt control device 4 becomes active, and an interrupt request 7 is issued.
At point S in Figure 2, the micro-
The processor starts processing rehijobs and memory fetches and instruction executions continue, resulting in maximum power consumption.

As described above, according to the above embodiment, by varying the frequency of the /S10penotem clock according to the state of the state discriminator microprocessor, it is possible to save a large amount of power when executing the halt instruction. It has the advantage of being able to

Further, according to the above-mentioned embodiment, a microprocessor system can be constructed by using the system clock of the microprocessor at the maximum operating frequency during normal operation, thereby reducing the processing speed.

Effects of the Invention As is clear from the above embodiments, the present invention has the following effects.

(1) Since the system clock of the microprocessor is made variable, during normal operation it operates at the maximum system clock frequency and processing speed does not decrease.

(2) Similarly, when the microprocessor executes a halt instruction, the system clock frequency is reduced, making it possible to save sufficient power.

[Brief explanation of the drawing]

FIG. 1 shows a micro-11 in an embodiment of the present invention.
-7 A schematic block diagram of the processor system device. Fig. 2 is a timing diagram showing access to the storage device of the device and halt instruction execution. Fig. 3 is a diagram of the relationship between operating frequency and power consumption in 0MO3. Fig. 4 5 is a schematic block diagram of a conventional microprocessor system device, and FIG. 5 is a timing diagram showing access to a storage device and execution of instructions in the conventional device. 1...Microprocessor, 2. Storage device,
3...Peripheral device, 4...Interrupt control device,
5...System clock variable device, 6...System bus, 7...Interrupt request signal, 8...Storage device read signal, 9...System clock, 1
0...Status determination device, 11...Interrupt IR○~
7.21...Microprocessor, 22...Storage device, 23...Peripheral device, 24...Interrupt controller, 25...System clock generator, 26... ...System bus, 27. =, 1
, tll) Interrupt request f1, 28...Storage device read signal, 31...Interrupt IRO~7°

Claims (1)

[Claims] A microprocessor, storage devices and peripheral devices connected to the microprocessor's system bus signals, a system clock variable device for varying the microprocessor's system clock, and a system clock variable device for varying the microprocessor's operating state. and an interrupt control device that prompts the microprocessor to restart, and slows down the system clock while the microprocessor is executing a halt instruction to save power of the microprocessor. A power saving control device for a microprocessor, characterized in that when the halt instruction of the microprocessor is canceled by the interrupt control device, the system clock is returned to the cycle before the execution of the halt instruction.