JPH0478909A - Personal computer and microprocessor - Google Patents

Abstract

PURPOSE:To eliminate the need of a program change related to a keyboard input by placing a cache memory of a small capacity between a microprocessor and a main memory, so that it is judged that the microprocessor is in a waiting state, when the cache memory is hitting. CONSTITUTION:When a cache memory 3 is hitting, and when a halt detecting circuit 7 detects execution of a halt instruction of a microprocessor 1, a clock switching circuit 4 makes a frequency of a clock of the microprocessor 1 low, and when the cache memory 3 is not hitting, and when the microprocessor 1 is released from a halt state by an external factor after the halt instruction is executed, the clock switching circuit 4 makes the frequency of the clock of the microprocessor 1 high. That is, a waiting state is detected by a hardware. In such a way, it becomes unnecessary to change a program related to a key input.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to reducing the power consumption of laptop computers and the like. The system detects this and lowers the clock frequency of the microprocessor when it is in a wait state, thereby reducing power consumption.

[Conventional technology]

Recently, laptop computers, especially very small, thin, and light laptop computers called notebook or book type, have rapidly become popular. All of these can be operated on batteries, and in addition to size and weight, the length of time the laptop can operate on battery power is a very important factor for laptop computers.

Under these circumstances, computer manufacturers are working to reduce the power consumption of their devices in order to extend battery life as much as possible. A currently widely used method for reducing the power consumption of devices is called standby mode.This means, for example, that when a microprocessor is waiting for a key to be pressed from the keyboard, If it does not turn on for a certain period of time (for example, 3 minutes,
The microprocessor determines that the operator is temporarily suspending key power, and the microprocessor simply waits for key power until the operator resumes key power. Therefore, at this time, the computer is placed in standby mode. This method sets the device to a mode that does not consume much power.

In standby mode, the clock frequency of the microprocessor is lowered, or the clock of the microprocessor is stopped in some cases. It also turns off the backlight of the LCD display and stops the hard disk drive motor. In this way, the power consumption of the device is reduced in standby mode.

This specification does not cover much of the individual techniques for reducing power consumption in standby mode (lowering the clock frequency of the microprocessor, turning off the LCD backlight, stopping the hard disk motor, etc.). do not have.

The present invention relates to a method for detecting the waiting state of a microprocessor to enter standby mode.

Taking input from a keyboard as an example, we will clarify the differences between the conventional method and the method of the present invention. Figure 3 shows a general key manual processing method in the form of a flow chart. , which is widely used in desktop computers. This means that the microprocessor will continue to wait until the key power is available, and when the key power is available, it will process the key power.D.If there is no key power for several hours, the microprocessor will simply wait. Put it away. This method is fine for devices where power consumption is not a concern, such as desktop computers, but it is very problematic for battery-powered laptop computers. For example, if an operator on a laptop computer temporarily suspends key work, the laptop computer will simply wait for key work until the key work is resumed. , even though no useful work is being done during that time, electricity is being consumed at a normal pace. It is possible to detect such a key-manpower state (a relatively long waiting state, such as an interruption of the operator's key-manpower work), and to reduce consumption as much as possible since the equipment is not doing any useful work in this state. The idea of keeping power consumption low was born. This mode in which power consumption is kept low is generally called a power save mode or standby mode. In this specification, this mode will be referred to as standby mode. In the standby mode, the microprocessor does not perform any useful work, so there is no problem in lowering or, in some cases, stopping the clock of the microprocessor, thereby reducing power consumption. In standby mode, no display is required and the hard disk drive is not used, so the backlight of the liquid crystal display is turned off and the hard disk drive motor is stopped to reduce power consumption.

Figure 2 shows a flowchart of the key input processing method for a laptop computer that incorporates the concept of standby mode, which has been explained above.This method has been the most widely used so far (see Figure 2 is a typical example of the conventional technology). FIG. 2 will be briefly explained. If there is a key power within 3 minutes after starting to wait for the key power (3 minutes is not particularly limited, but it usually feels very difficult to use if it is too short), no special processing will be performed. , as soon as the key power is applied, the processing for the key power is performed. However, 3
Set the device to standby mode if there is no human power. (Individual processing for reducing power consumption in standby mode will not be discussed.) In standby mode, the power consumption of devices is kept low. If there is key human power in standby mode, the standby mode is first canceled and then processing for the key human power is performed. As shown in Figure 2 above, by detecting a state in which the key is waiting for human power (a state in which there is no key power being applied for more than 3 minutes) and setting the device to standby mode, the power consumption of the device can be reduced. This is the conventional technique.

[Problem to be solved by the invention]

The conventional method shown in FIG. 2 has several drawbacks.

Let's sort this out first.

The first problem is that the program related to keyboard input must be changed.

FIG. 3 is the basic key manual processing, but in order to create the flow as shown in FIG. 2, it is necessary to change the program.

The second problem is that if an application program (such as a word processing software) were to perform key manual processing directly by itself, it would be possible to use it via BIO3 (Basic Output System) or DO3 (Disk Operating System). If you directly access the keyboard interface hardware yourself, even if the computer manufacturer configures the BIO8 related to keystrokes as shown in the flowchart in Figure 2, this BIO8 will not be called and the computer will enter standby mode. The point is that it does not.

The third point is that the corresponding program must be changed for each input/output device.

Figure 2 only shows the part related to the keyboard; for example, a flowchart as shown in Figure 2 must be created for each input/output device, such as a mouse, printer, modem, etc., and the program must be changed.

The fourth fish takes a long time to enter standby mode (
(3 minutes in the case of FIG. 2), the power consumption during that time cannot be saved.

[Means to solve the problem]

A means for solving the above-mentioned problems of the conventional technology is to detect the waiting state using hardware.

(Traditionally, this was done using software.) This method places a small-capacity cache memory between the microprocessor and main memory, and when the cache memory is hit, the microprocessor is determined to be in a waiting state.

The wait state detection method of the present invention is not limited to keyboard input, but is a wait state detection method for general input/output devices.

Hereinafter, the present invention will be explained in detail according to examples.

〔Example〕

FIG. 1(a) shows an embodiment of a personal computer according to the present invention. 1 is a microprocessor D, and 2 is a main memory in which instruction codes for the microprocessor 1 are stored. 3 is a cache memory D, and the cache memory capacity is 64 bytes. Cache memory No. 3 also includes all control circuits. The cache memory 3 can be partially disabled, and the effective cache memory capacity can be freely changed from 0 hide to 64 bytes. The cache method is a tie reflex 1-mapping method. (Cache methods include direct mapping method, two-way set associative method, N-way set associative method, full set associative method, etc., but explanations of each method will be omitted. 5 is a hit signal for the cache memory 3, and D indicates that the cache memory is hit. 7 is a halt detection circuit D,
It is detected that the microprocessor 1 has executed a halt instruction (stop instruction). After executing the halt instruction, the microprocessor 1 remains in the halt state until an interrupt occurs. 8 is a halt detection signal D, which indicates that the microprocessor 1 is in a halt state, 4 is a clock switching circuit D, and 6 is a clock signal of the microprocessor. HIT signal 5 is HIT signal 1 of cache memory
- and when the halt detection signal 8 indicates the halt state of the microprocessor, the clock switching circuit 4 lowers the frequency of the microprocessor clock signal 6 (to IMHz, for example), and when the microprocessor 1 is in the halt state. state and when the cache memory is not hit, that is, when there is a miss, increase the frequency of the clock signal 6 (for example, 12MH).
z). When the clock during normal operation is 12MHz, when the cache memory 3 is at 1-1, and when the microprocessor 1 is in a halt state, the clock is set to IM.
You can see that it is lowered to Hz. cache memory 3
Although the clock frequencies at the time when the microprocessor 1 is suspended and when the microprocessor 1 is halted are both IMHz, they do not have to be the same. For example, the clock frequency during normal operation may be 12 MHz, the clock frequency when the cache memory 3 is hit may be IMHz, and the clock frequency during halt state may be 100 KHz.

Cache memory 3 is SRAM (static RAM)
The main memory 2 is composed of DRAM (dynamic RAM). The configuration is explained above,
Next, the operation shown in FIG. 1(a) will be briefly explained. When the microprocessor (hereinafter referred to as HPU) 1 attempts to read an instruction or data from the main memory 2, it is first checked to see if the same data exists in the cache memory 3. If there is an instruction or data to be read in the cache memory 3, it is said that the cache memory has been hit, and the MPUI reads the instruction or data from the cache memory 3 and does not access the main memory 2. At this time, the hit signal 5 becomes high level (
), the clock switching circuit 4 is MP
Lower U's clock signal 6 to IMHz. If there is no instruction or data to be read in cache memory 3, it is said that there has been a cache memory miss, and M
The PUI reads instructions or data from the main memory 2. At this time, the contents of the cache memory 3 are also updated at the same time. (Instructions or data read from the main memory 2 by the MPUI are also written to the cache memory 3 at the same time.) At this time, Hiratoi 4 and 5 become low level (indicating a miss), and the clock switching circuit 4 Clock signal 6 is assumed to be 12 MHz.

When the MPUI executes the Hall 1 command, the halt detection circuit 7 detects this and the halt detection signal 8 becomes high level. At this time, the clock signal 6 of the microprocessor 1 becomes IMHz. The clock switching circuit 4 sets the clock signal 6 to IMHz when at least one of the hit signal 5 and the halt detection signal 8 is at a high level, and sets the clock signal 6 to 12 MHz when both are at a low level.

The operation of FIG. 1(a) has been explained above.
The relationship between a) and the waiting state detection method will be explained. Figure 1 (a) shows the detection of a wait state using hardware. First, we will analyze the flow of the most basic key human processing in Figure 3 and develop it in a form that is easy to understand at the hardware level. . There are two main methods that can be considered to implement the part of FIG. 3 that is waiting for key human power (part A in FIG. 3). One method is to use interrupts, and the other is to loop while checking the status. First, let's consider how to use interrupts. Methods using interrupts can be further divided into two methods. One method is to have an interrupt while the program is looping, and the other is to execute a halt instruction and wait for an interrupt in the halt state. A flowchart for waiting for an interrupt while looping is shown in FIG. 4(a), and a flowchart for waiting for an interrupt in a halt state is shown in FIG. 4(b). In FIG. 4(a), first, key interrupts are enabled manually, and then the program itself waits for the interrupt while looping. And when there is an interrupt, the interrupt processing routine (processing for key human power)
Branch into.

In FIG. 4(b), the microprocessor enters a halt state by executing a halt command after enabling a key manual interrupt. In this state, the controller waits for a key human input interrupt, and when an interrupt occurs, branches to the interrupt processing routine (processing for key human input).

Next, a flowchart of a method of looping while checking the status is shown in FIG. 4(C). Here, without using interrupts, the program loops while checking the status of the key power, and continues in a loop until the key power is detected. When key human power is detected, this loop is exited and processing for the key human power is performed.

There is a common point between FIG. 4(a) and FIG. 4(C). It is part A1 in Figure 4(a) and A in Figure 4(C).
In part 3, the point is that both programs are in a loop (and it is a small loop), and the real idea is to detect the wait state of the microprocessor by detecting this program loop with hardware. This is the point of the invention. Also, as shown in FIG. 4(b), there are cases where the microprocessor is waiting in a halt state, so in this case, the halt state of the microprocessor is detected by a halt detection circuit. The actual program for part A1 in Figure 4(a) and part A3 in Figure 4(C) will probably include a few more processes (instructions) other than those shown here, but in any case, it will be a small loop. (It is 64 bytes or less). This loop is detected by the direct mapping cache memory 3 with content fi (64 bytes) as shown in Figure 1(a).
This is an example. A1 in Figure 4(a) and Figure 4(C)
Since A3 is a loop of 64 bytes or less,
When this loop is executed around -, the instruction inside the loop (
All instructions (instructions) are stored in the cache memory 3 shown in FIG. 1(a), and the cache memory is hit from the second loop onwards. The cache memory will continue to be hit until the loop is exited. In other words, when the cache memory 3 in FIG. 1(a) is hit, the hit signal 5 is at a high level),
It can be determined that the microprocessor 1 is in a waiting state and in a loop. At this time (when it is a human) Figure 1 (
In a), lower the clock 6 of microprocessor 1,
I'm trying to lower power consumption.

However, one caution is necessary here. The question is whether the cache memory 3 shown in FIG. 1(a) may be hit even when the microprocessor 1 is not in a waiting state. In order to prevent this, it is preferable to make the memory capacity of the cache memory 3 as small as possible. A program that performs repeated processing takes the form of a loop, but in this case, the processing instructions are included in the loop, so the loop is considerably longer than the waiting loop shown in Figure 4. Become. The memory capacity of the cache memory 3 in FIG. 1(a) is variable D, and by adjusting this, it is possible to separate the loop for repeated processing and the loop for waiting. That is, the memory capacity of the cache memory may be set smaller than the loop for repeated processing and longer than the loop for waiting. In this way, the cache memory 3 will be hit when the loop is in the waiting state, but it will not be hit when the program performs repeated processing.

The above is the explanation of the embodiment shown in FIG. 1(a), and finally, the cache memory 3 shown in FIG. 1(a) will be mentioned.

The cache memory 3 shown in FIG. 1(a) is completely different from how a normal cache memory is used. Cache memory is usually used to increase the speed of personal computers and to increase the hit rate as much as possible. Therefore, we try to increase the memory capacity as much as possible. On the other hand, the cache memory 3 in the present invention is used to reduce the power consumption of the basal computer.
, I try to avoid hits as much as possible except when looping in the wait state.

(If possible, it would be better if there were no hits at all except in the loop in the waiting state.) Therefore, the memory capacity is also quite small.

FIG. 1(b) shows a second embodiment of the present invention.
Compared to a), there is no halt detection circuit.

Therefore, the clock cannot be switched when the microprocessor is in a halt state.

FIGS. 1C, 1D, and 1E each show an embodiment of a microprocessor according to the present invention. Figure 1 (C)
100 is a microprocessor D according to the present invention, which in addition to the functions of the conventional microprocessor 1 includes a small-capacity cache memory 3. Figure 1 (d
), 1゜1 is a microprocessor D according to the present invention, which has, in addition to the functions of the conventional microprocessor 1, a small-capacity cache memory 3 and a clock switching circuit 14.
Contains. In FIG. 1(e), 102 is a microprocessor D according to the present invention, which includes, in addition to the functions of the conventional microprocessor 1, a small-capacity cache memory 3, a halt detection circuit 7, and a clock switching circuit 4. There is. The personal computer shown in FIG. 1(a) and the personal computer shown in FIG. 1(e) have exactly the same functions.

Similarly, the personal computer in FIG. 1(b), the personal computers in FIG. 1(C), and the personal computers in FIG. 1(d) have exactly the same functions.

〔Effect of the invention〕

According to the present invention, all of the four drawbacks of the prior art mentioned above in "Problems of the Prior Art" can be solved.

That is, (1) Since the wait state is detected by hardware, there is no need to change the program related to key manual operation.

(2) Even if the application program is directly processing key input, the wait state is detected by the hardware.
Therefore, since standby mode can be set only by hardware, standby mode is guaranteed for all application programs.

(3) The embodiments shown in FIGS. 1(a) to (e) are valid for each input/output device. That is, in the embodiments of FIGS. 1(a) to 1(e), it is possible to detect not only the waiting state of a key but also the waiting state of other IO devices without any particular distinction.

(4) Since wait state detection is performed by hardware, standby mode can be set immediately. Also, when entering the wait state, the cache memory continues to be hit,
Therefore, during this time, the microprocessor only accesses the cache memory and does not access the main memory. Normally, the main memory is a RAM with very high power consumption, whereas the cache memory is a SRAM with low power consumption, so the power consumption of the cache memory when it is hit, that is, in a waiting state, is quite small.

Furthermore, by including a cache memory in a microprocessor, the following effects occur.

In other words, (5) the main memory cannot be accessed in the wait state, and a microprocessor that includes cache memory does not drive the microprocessor's input/output terminals (address bus, data bus, etc.) in the wait state. , compared to those with external cache memory, power consumption is extremely low.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are diagrams showing an embodiment of a personal computer according to the present invention. Figure 1(c), (
d) and (e) are diagrams showing embodiments of a microprocessor according to the present invention. FIG. 2 is a flowchart showing a conventional method (waiting state detection method). FIG. 3 is a basic flowchart of key manual processing. Figure 4 (a
), (b), and (C) are diagrams analyzing key manual processing. 1... Microprocessor (conventional) 2... Main memory 3... Cache memory 4, 14... Clock switching circuit 5... Hit signal 6... Microprocessor clock signal 7... Halt detection circuit 8... Halt detection signals 100, 101, 102... Microprocessor or higher according to the present invention Applicant: Seiko Epson Corporation Representative Patent attorney: Kizobe Suzuki (Q) Figure (d) Figure 4 (C)

Claims (1)

Scope of Claims: (1) A, a microprocessor; B, a main memory for storing instructions executed by the microprocessor; C, a small-capacity cache memory for the main memory; and D, a halt instruction by the microprocessor. and a clock switching circuit that switches the frequency of a clock signal for the microprocessor, wherein the halt detection circuit detects when the cache memory is hit, and the halt detection circuit detects when the cache memory is hit. When the circuit detects execution of a halt instruction in the microprocessor, the clock switching circuit lowers the frequency of the clock of the microprocessor, and when the cache memory is not hit, and when the microprocessor detects execution of a halt instruction, the clock switching circuit lowers the frequency of the clock of the microprocessor. 1. A personal computer, wherein the clock switching circuit increases the frequency of a clock of a microprocessor when the computer is released from a halt state. (2) The cache memory is a direct mapping type cache memory, the memory capacity is 64 bytes or less, and the effective cache memory capacity can be made variable by disabling a part of the cache memory. 2. A personal computer according to claim 1. (3) A microprocessor characterized by being equipped with a direct mapping type cache memory having a capacity of 64 bytes or less, and having a hit signal of the cache memory as an output terminal. (4) It has a direct mapping type cache memory with a capacity of 64 bytes or less and a clock switching circuit for switching the operating clock frequency, and when the cache memory is hit, the operating clock frequency is lowered to prevent the hit from occurring. A microprocessor characterized by increasing its operating clock frequency when it is not running.