JPH0315371B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides, for example, when performing transport control using a power line, by using a zero-cross signal of the power supply between a control device and a controlled device, a time period can be established. The present invention relates to a zero-crossing signal detection circuit that can perform

A specific circuit of a conventional zero-crossing signal detection circuit is shown in FIG. In this circuit, the input voltage is a predetermined value V _th
It is comprised of a gate section A that outputs an H level voltage signal only during the following times, and a constant pulse width verification circuit section D that removes signals less than a predetermined pulse width from the output of the gate section A. Therefore, if a full-wave rectified waveform of a commercial power supply with superimposed noise as shown in Fig. 2a, a is input to the input end 6 of the inverter 5 constituting the gate section A, then The inverter 5 outputs an H level voltage signal as shown in _FIG . Note that the voltage signal shown in c in Figure 2b is as follows:
A noise pulse with a pulse width smaller than one period of the clock pulse for width verification shown in c of the same figure.
It goes without saying that the noise pulse shown in FIG. 2B is caused by the power supply noise, which is a noise pulse having a pulse width larger than one period of the clock pulse. The H level voltage signal output from the gate section A is sampled by the width verification clock pulse and read into the D-flip-flop 7 of the constant pulse width verification circuit section D. Therefore, this D-flip-flop 7
The output of is shown in Figure 2d, and the output of
- The output of the flip-flop 7 is sampled with a width verification clock pulse and read into another D-flip-flop 8. Therefore, the output of another D-flip-flop 8 is as shown in FIG. 2e. The outputs of the respective flip-flops 7 and 8 are input to an AND gate 9, and the output of this AND gate 9 becomes the output of the constant pulse width verification circuit D as shown in FIG. 2F. That is, noise pulses having a pulse width less than one period of the clock pulse for width verification are removed, and the so-called zero cross signal generated in synchronization with the cycle of the power supply when the power supply voltage is near the zero level is detected by the AND gate 9. It is output from the output end 11. In addition, 10
is a clock pulse receiving terminal for width verification. However, in the conventional example described above, as shown in FIG. 2(f), it is not possible to remove noise pulses having a width of one cycle or more of a clock pulse for width verification. Therefore, by increasing the period of the clock pulse for width verification, it is possible to remove wide pulses, but if the period is increased beyond a certain point, the position of the zero-crossing signal will shift, making it impossible to use it as a periodic signal. As described above, in the conventional circuit as shown in FIG. 1, it is not possible to completely remove wide pulses of noise components, so there is a problem in extracting the zero-cross signal from the power supply.

In view of the above-mentioned points, it is an object of the present invention to provide a zero-crossing signal detection circuit capable of obtaining a zero-crossing signal that is not affected by power supply noise.

An embodiment of the present invention will be described with reference to the drawings. A and D are a gate section consisting of an inverter 5 and a constant pulse width verification circuit section similar to those explained in the conventional example. B is H of constant pulse width verification circuit section D
A timing section that receives a voltage signal of a certain level and outputs a timing pulse having a pulse width Tp after a certain delay time Td as shown in FIG. 4c. It can be configured with a gate 16. Further, C is a latch section which receives the output of the constant pulse width verification circuit section D and the output of the timing section B, and includes, for example, two NOR gates 12, as shown in FIG.
In this latch section C, when an H level voltage signal is input to the input of the NOR gate 13, the outputs of the NOR gates 12 and 13 become H.
When a high level voltage signal is input to the input of the NOR gate 12, the output becomes low level. Note that the output of the AND gate 16 of the timing section B is input to the NOR gate 12, and the constant pulse width verification circuit section D is input to the NOR gate 13.
The output of is input. Then, input the output of the latch section C to the reset terminal 17 of the counter 15,
The count of the counter 15 is reset. In other words, the timing section B and the latch section C output an output that prohibits the output of the H-level voltage signal from the gate section A for a fixed period shorter than a half cycle of the commercial power supply from the time when the H-level voltage signal from the gate section A is output. It constitutes a prohibition circuit section.

When the output of the constant pulse width verification circuit section D shown in FIG. 4B is input to the NOR gate 13 of the latch section C, the output of the latch section C becomes H level, and the counter 15 is reset by this output. Counter 15 begins counting the standard clock. Then, after a certain delay time Td shown in FIG. 4c has elapsed, the output of the AND gate 16 becomes H level. Therefore, the output of latch section C becomes L level as shown in FIG. 4d. After that, the output of the constant pulse width verification circuit section D becomes H level, and the same operation as described above is repeated.

By the way, when the timing pulse with the pulse width Tp shown in FIG. while,
Noise pulses caused by power supply noise can be completely removed. However, the equation cannot be completely satisfied due to variations in accuracy of the timing part B, and therefore it is necessary to provide a margin time Te as shown in FIG. 4c. For example, when the power supply frequency is 60 Hz, the period Tc of the zero-cross signal is 8.3 msec, so the delay time Td needs to be selected to be about 8.0 msec. At this time, the output inhibit circuit can remove noise between Td + Tp, but the margin time
During Te, no countermeasures are taken against the noise pulse. Therefore, in this embodiment, a constant pulse width verification circuit section D is provided so that noise pulses of less than one period can be removed even during the above-mentioned margin time Te. Therefore, it is not affected by power supply noise during the entire period, and therefore a zero-crossing signal that is not affected by noise can be obtained.

As described above, the present invention includes a gate section that generates an output while a full-wave rectified voltage of a commercial power supply is input and a voltage below a predetermined value close to zero level is input, and a a constant pulse width verification circuit section that removes the signal from the constant pulse width verification circuit section, and prohibiting the output of the output signal of the constant pulse width verification circuit for a fixed period shorter than a half cycle of the commercial power supply from the time of outputting the output signal of the constant pulse width verification circuit section. The output prohibition circuit section suppresses the output signal of the constant pulse width verification circuit for a fixed period shorter than half a cycle of the commercial power supply from the point of output of the output signal of the constant pulse width verification circuit section. By prohibiting the output of the output, even if noise due to surges such as lightning or relays is superimposed on the commercial power supply during the certain period, the noise pulse can be removed by the output prohibition circuit. By the way, due to variations in circuit precision in the output prohibition circuit section, the fixed period during which the output of the constant pulse width verification circuit section is prohibited varies. Therefore, the margin time is set so that the output prohibition period is shorter than a half cycle of the commercial power supply. It is necessary to provide During this margin period, noise cannot be removed by the output prohibition circuit, but since a constant pulse width verification circuit section is provided that removes signals less than a predetermined pulse width from the output of the gate section, noise can be eliminated during the margin period. Can be removed. Therefore, it is possible to obtain a zero-cross signal that is not affected by noise at all during the entire period, and is therefore not affected by noise.

[Brief explanation of the drawing]

FIG. 1 is a specific circuit diagram of the conventional example, FIG. 2 is an explanatory diagram of the same operation as above, FIG. 3 is a block circuit diagram of an embodiment of the present invention, FIG. 4 is an explanatory diagram of the same as above, and FIG. FIG. 3 is a specific circuit diagram of an output prohibition circuit. A is a gate section, B is a timing section, C is a latch section, and D is a constant pulse width verification circuit section.

Claims (1)

[Claims] 1. A gate section that generates an output while the full-wave rectified voltage of the commercial power supply is input and a voltage below a predetermined value close to zero level is input, and a constant pulse that removes signals less than a predetermined pulse width from the output of the gate section. a width verification circuit section; and an output prohibition circuit section that prohibits output of the output signal of the constant pulse width verification circuit for a fixed period shorter than a half cycle of the commercial power supply from the time when the output signal of the constant pulse width verification circuit section is output. A zero-cross signal detection circuit comprising: