JPH03154902A - Digital controller - Google Patents

Abstract

PURPOSE:To shorten the operation time and to prevent a wind-up phenomenon by changing the limit value of an input limiter in accordance with the output of an integrator of an advance/delay circuit and limiting the output of the advance/delay circuit to the prescribed value. CONSTITUTION:The algorithm of an advance/delay circuit 7 is composed of an addition circuit 10 consisting of a proportion circuit and an integrated circuit 9. An input limiter 14 is provided to the input of the circuit 10. Then the limit value of the limiter 14 is changed to the value obtained by dividing the differ ence between the limit value of an output limiter 11 and the output of the circuit 9 by the gain of the circuit 8. Under such conditions, the sum of outputs of both circuits 9 and 8 is always equal to the limit value of the limitter 11 despite of application of a large input signal. Thus, the output of the circuit 9 never exceeds the limit value despite application of a long time. Therefore, the output of the circuit 7 immediately gets out of the output limit value and changes in response to the input signal when the input signal is set again to its small value. As a result, the operating time is shortened and at the same time a wind-up phenomenon is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a digital control device using a lead/lag circuit as a stabilizing circuit of a control system.

(Prior Art) FIG. 3 shows an example of a conventional analog lead/lag circuit with a limit. In this example, the input impedance of operational amplifier 1 is resistor 2, and the feedback impedance is a parallel configuration of a series circuit of resistor 3, resistor 4, and capacitor 5. Furthermore, the purpose of limiting the output voltage of operational amplifier 1 is to This circuit includes a Zener diode 6.

When a voltage is applied to the input of this circuit, operational amplifier 1 outputs a voltage whose polarity is opposite to the input voltage, and sinks current from the input of this circuit through the input impedance and feedback impedance (if the input voltage is negative) It is well known that the operational amplifier 1 always operates so that the input voltage becomes zero due to the impedance drop of the current flowing through the input impedance. In this lead/lag circuit 7, when the current flows to the output side of the operational amplifier 1 through the feedback impedance flowing through the resistor 2, an output voltage is generated due to the current drop in the feedback impedance. The feedback impedance changes, and eventually charging of the capacitor 5 is completed, the shunting of the resistor 4 is eliminated, and the current is amplified by the ratio of the resistors 2 and 3 (referred to as a steady gain).

Next, let us consider the operation when there is a large voltage change at the input of this circuit and the output of the operational amplifier 1 is saturated. A large voltage is applied to the input of this circuit, and operational amplifier 1
When the output voltage reaches the characteristic voltage of the Zener diode 6, current also flows through the Zener diode 6, and the output of the operational amplifier 1 is limited to the characteristic voltage (referred to as limit 1 to voltage) of the Zener diode 6.

When the output of operational amplifier 1 is voltage limited to limit 1,
Since the voltage across the series circuit of the resistor 4 and the capacitor 5 also becomes the limit voltage, the voltage across the capacitor 5 changes from the limit 1 to the voltage with a first-order lag.

After that, when the input voltage returns to the value obtained by dividing the limit voltage by the steady-state Cain, the current flowing through resistor 2 decreases, so even if all of that current flows through resistor 3, it will not reach the limit I voltage. As can be seen from the figure, the output of the operational amplifier 1 had a characteristic of immediately exceeding the limit voltage.

In recent years, the number of digital devices has increased, and in order to replace systems similar to analog devices, there are cases in which a limit parallel lead-lag circuit is imitated. FIG. 4 shows an example of a block diagram of limit 1 to lead/delay circuits in a digital device.

Here, the function of the lead/lag circuit 7 is the addition of the proportional gain (Tl/T2, referred to as the proportional circuit 8) and the -order lag (consisting of an integrator and negative feedback, referred to as the integrating circuit 9) as shown in the following equation. expressing.

Here, T□: Advance time constant, T2: Delay time constant S nira plus operator When a large signal is applied to the input of this circuit, the output of the proportional circuit 8 and the output of the adder circuit 10 of the integral circuit 9 are immediately The output is limited by the output limiter 11, but at this time, the integration circuit 9 integrates according to the input signal regardless of the output being limited, so the larger the input signal and the longer the application time, the more the component circuit The output of 9 also increases. Therefore,
If a large input signal is applied for a long time, even if the input signal returns to near zero, the output signal will be the output of the integrating circuit 9 and the limit will not be exceeded immediately. This phenomenon is referred to as wind-up J (2-phenomenon), and the output 4n has a characteristic that it does not follow the human input signal at all, so if this phenomenon continues for a long time, problems will occur in the control circuit.

Next, as a method to prevent this windup phenomenon, an example of a block diagram of the algorithm we considered is shown in Figure 5.
This method will be explained. In this system, the lead/lag circuit 7 is configured with a forward proportional circuit (1x gain) 12 and the negative feedback of an incomplete differentiation circuit 13 as completely equivalent functions, and the output limiter 11 of the lead/lag circuit 7 is incomplete. Since the manual power of the differentiating circuit 13 is also limited, the wind-up phenomenon described above does not occur at all.

(Problem to be Solved by the Invention) However, in this circuit, the closed loop circuit consisting of the proportional circuit 12 and the incomplete differential circuit 13 is a circuit with no delay, so when realizing this block in a digital system, it is difficult to perform calculations. If the time increments used are large, problems occur with large fluctuations in output. That is, in general, a small first-order delay is provided in the proportional circuit 12 to reduce the time increments for calculation. However, if the time increments are made smaller, the calculation time becomes longer, which is a big problem especially in digital control devices that need to process in real time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a limit parallel lead/delay circuit that does not require a large amount of calculation time and is completely free from the windup phenomenon in a digital control device that requires processing in real time.

[Structure of the invention]

(Means for Solving the Problems) The present invention consists of an algorithm for a lead-lag circuit by adding a proportional circuit and an integral circuit, an input limiter is provided at the input of this circuit, and the limit value of the output limiter and the output of the integral circuit are The limit value of the input limiter is changed to a value obtained by dividing the difference between the two by the gain of the proportional circuit.

(Function) In this case, even when a large input signal is applied, the sum of the output of the integrator circuit and the output of the proportional circuit is always equal to the output limiter limit of 1 to 1.
Even if a large input signal is applied for a long time,
The output of the integrating circuit never exceeds the limit 1~ value. Therefore, when the input signal returns to its original small value, the output of the lead/lag circuit immediately drops to the output limit 1 and changes in accordance with the input signal. In other words, it is possible to realize a characteristic completely free from the wine 1-up phenomenon, similar to the conventional analog limit parallel lead/lag circuit.

(Example) An embodiment of the present invention will be described below with reference to FIG.

In the configuration of the present invention, the algorithm of the lead/lag circuit 7 is formed into a proportional circuit (Tyo/T2) 8 and an integral circuit, and an input limiter 14 and an output limiter 1 are provided at the input and output of this circuit, respectively.
1, and the limit value of the input limiter 14 is always set to the value obtained by dividing the difference between the limit value of the output limiter 11 and the output of the integrating circuit 9 by the gain (T, /T,) of the proportional circuit 8. There is.

Here, the upper and lower limits of the input limiter 14 are values obtained by dividing the difference between the upper and lower limits of the output limiter 11 and the output of the integrating circuit 9 by the gain (T□/T2) of the proportional circuit 8.

The operation of such an algorithm will be described next. When the input signal is small and the output of the integrator circuit 9 is also small, the deviation between the output limiter 11 limit value and the integrator circuit 9 is large, and the deviation is converted into the gain (T) of the proportional circuit 8.
Since the value divided by 1/T2) also becomes large, the limit value of the input limiter 14 is also set to a large value. Therefore, the input signal is not limited by the input limiter 14 and operates only through the lead/lag circuit 7.

On the other hand, when a large input signal is applied and the output of the integrating circuit 9 becomes large, the sum of the output of the integrating circuit 9 and the output of the proportional circuit 8 tends to exceed the limit value of the output limiter 11, but the output limit value The limit value of the input limiter 14 is set to the value obtained by dividing the deviation of the output of the integrating circuit 9 by the gain (T1/T2) of the proportional circuit 8, and the input signal is limited. Therefore, the sum of the output of the integrator circuit 9 and the output of the proportional circuit 8 is equal to the value of limit 1 of the output limiter 11, and as the output of the integrator circuit 9 increases, the input signal is further limited, and the integrator circuit always The sum of the output of the proportional circuit 9 and the output of the proportional circuit 8 is equal to the limit value of the output limiter 11.

In this state, the sum of the output of the proportional circuit 8 and the output of the integral circuit 9 is equal to the limit 1 of the output limiter 11, so if the input signal returns to its original small value from this state, at least the proportional circuit Since the output of 8 immediately becomes small, the output of this circuit is.

The limit value of the output limiter 11 is extracted according to the input signal. In other words, it has a characteristic that is completely free of wind-up phenomenon, similar to the conventional analog type limit parallel advance/delay circuit.

In the above embodiment, the integrating circuit 9 is configured with a forward-facing integrator 15 and a first-order delay with negative feedback with a gain of 1, but as shown in FIG. The subtraction circuit 18 of the perfect differentiation circuit 17 can also be used. In this case, the above-mentioned characteristics can be obtained by changing the input limit value based on the difference between the output limit value and the output of the subtraction circuit 18.

The point is, if we analyze the lead/lag circuit 7, an integrator is definitely required to realize the circuit, but by changing the input limit value based on the signal corresponding to the output of the integrator, the above-mentioned characteristics can be achieved. That's what you get.

Note that in this algorithm, the output limiter 11 is provided to simplify the explanation, and is used to set target values (Lvl and LY2) that limit the output of the lead/lag circuit 7.
This output limiter 11 is not essential.

Furthermore, since the present invention is applied to a digital device, it is easy to change the limit value of the input limiter according to the output of the integrator.

〔Effect of the invention〕

As described above, according to the present invention, even if a large signal is applied to the input of the lead-lag circuit for a long time in the digital control device 100- that requires processing in real time, the output of the lead-lag circuit It is possible to provide a limit 1 to lead/lag circuit that can change according to an input signal without causing a windup phenomenon.

[Brief explanation of the drawing]

FIGS. 1 and 2 show a limit 1 according to an embodiment of the present invention.
- Figure 3 is a diagram showing the configuration of a conventional analog sumit lead/delay circuit, and Figures 4 and 5 are digital sumit! - It is a block diagram of a parallel advance/delay circuit. 1 - Operational amplifier 5... Capacitor 7... Lead/lag circuit 9... Integrating circuit 11... Output limiter 14... Input limiter 18... Subtraction circuit

Claims (1)

[Claims] It consists of a lead-lag circuit and a limiter that can change the limit value provided at the input of the circuit.By changing the limit value of the limiter according to the output of the integrator that constitutes the lead-lag circuit, the lead-lag circuit can be A digital control device that limits the output to a predetermined value.