JPH03155678A - Vertical mosfet - Google Patents
Vertical mosfetInfo
- Publication number
- JPH03155678A JPH03155678A JP1295931A JP29593189A JPH03155678A JP H03155678 A JPH03155678 A JP H03155678A JP 1295931 A JP1295931 A JP 1295931A JP 29593189 A JP29593189 A JP 29593189A JP H03155678 A JPH03155678 A JP H03155678A
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- epitaxial layer
- well region
- opposite conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
- H10D84/148—VDMOS having built-in components the built-in components being breakdown diodes, e.g. Zener diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/108—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having localised breakdown regions, e.g. built-in avalanching regions
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はアバランシェ降伏による破壊耐量を増大した縦
型ＭＯＳＦＥＴに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a vertical MOSFET with increased breakdown resistance due to avalanche breakdown.
（ロ）従来の技術
縦型ＭＯ５ＦＥＴは、第３図に示すように、底部に高濃
度Ｎ“型層（１〉を有するＮ−型シリコン基板〈２）を
ドレインとして、その表面上に所定の間隔でゲート電極
（ポリＳｉゲート） ＜３）が配置され、このゲート電
極（３）の下にチャンネル部を作るように基体り２）表
面にＰ型拡散領域（４〉とＮ“型ソース領域り５）を形
成したもので、ゲートへの電圧印加によってゲート下の
Ｐ型拡散領域（４）（チャンネル部）を通るドレイン電
流ＩＤｉを制御するようにＭＯＳＦＥＴを動作させるも
のである（例えば、特開昭６３−２６０１７６号公報）
、＜６）はＡｆｆｉ電極、（７）はガードリングである
。(b) Conventional technology As shown in Fig. 3, a vertical MO5FET uses an N-type silicon substrate (2) having a high concentration N'' type layer (1) at the bottom as a drain, and a predetermined layer on its surface. A gate electrode (poly-Si gate) <3) is arranged at intervals, and a P-type diffusion region (4>) and an N"-type source region are formed on the surface of the substrate so as to form a channel section under the gate electrode (3). The MOSFET is operated so that the drain current IDi passing through the P-type diffusion region (4) (channel part) under the gate is controlled by applying a voltage to the gate (for example, Publication number 63-260176)
, <6) is an Affi electrode, and (7) is a guard ring.
斯る縦型ＭＯＳＦＥＴは、大電流高速スイッチングが可
能なので、モータ制御、スイッチングレギュレータ、Ｃ
ＲＴ偏向用として多用されている。Such vertical MOSFETs are capable of high-current, high-speed switching, so they can be used in motor control, switching regulators, and C
It is widely used for RT deflection.
（ハ）発明が解決しようとする課題
しかしながら、第４図のようにリアクトル負荷（８〉を
ＭＯＳトランジスタ（９）でスイッチングする場合、コ
イル負荷（８）を遮断した瞬間に高い電流変化率ｄｉ／
ｄｔで大きなサージ電圧（１０）が発生し、このような
サージ電圧がＭＯＳトランジスタ（９）のソース・ドし
イン間に印加されることによりＭＯＳトランジスタ＜９
）は容易にアバランシェ領域まで印加される。(c) Problems to be Solved by the Invention However, when switching the reactor load (8>) with the MOS transistor (9) as shown in Fig. 4, the current change rate di/
A large surge voltage (10) is generated at dt, and this surge voltage is applied between the source and drain of the MOS transistor (9), causing the MOS transistor <9
) is easily applied up to the avalanche region.
アバランシェ領域まで印加されたＭｏＳトランジスタ（
９）は、第５図に示すように主にＰ型拡散領域（４）と
Ｎ−型基板（２）とが形成する接合ダイオード（１１）
がなだれ降伏することにより電流を吸収しようとする。MoS transistor applied up to the avalanche region (
9) is a junction diode (11) mainly formed by a P-type diffusion region (4) and an N-type substrate (2), as shown in FIG.
tries to absorb the current by avalanche breakdown.
ところが、ＭＯＳトランジスタ（９〉はＮ”ソース領域
（５）をエミッタ、Ｐ聖域牧領域（４）をベース、Ｎ−
型基体（２）をコレクタとする寄生トランジスタ（１２
）が不可避的に形成されてしまい、また、Ｎゝソース領
域（５）の底部はピンチ構造となるため、ソース領域（
５）とＰ型拡散領域（４）とのＰＮ接合はピンチ抵抗（
１３）により順バイアスされる電位差に容易に達して寄
生トランジスタ（１２）が導通してしまう。−旦寄生ト
ランリスタク１２）が導通すると、ＭＯＳトランジスタ
の阻止耐圧は寄生トランジスタ（１２）のｖｃｐ。まで
低下するので、アバランシェ電流が制御がきかない状態
で能動化したセルを流れ、結果的に素子が破壊されてし
まう現象がある。However, the MOS transistor (9) uses the N'' source region (5) as the emitter, the P sanctuary region (4) as the base, and the N-
A parasitic transistor (12) whose collector is the type substrate (2)
) is unavoidably formed, and since the bottom of the N source region (5) has a pinch structure, the source region (
5) and the P-type diffusion region (4) has a pinch resistance (
13), the parasitic transistor (12) becomes conductive due to the forward biased potential difference easily being reached. - Once the parasitic transistor (12) becomes conductive, the blocking voltage of the MOS transistor is vcp of the parasitic transistor (12). As a result, avalanche current flows uncontrollably through the activated cell, resulting in destruction of the device.
このように、従来の縦型ＭＯ３ＦＥＴはアバランシェ降
伏に対して無防備であり、破壊に至り易い欠点があった
。As described above, the conventional vertical MO3FET is vulnerable to avalanche breakdown and has the disadvantage of being easily destroyed.
（ニ）課題を解決するための手段
本発明は上記従来の欠点に鑑み成されたもので、ＭＯＳ
セルのＰ型拡散領域（２４）を囲むようにＰ型ウェル領
域（２５）を設け、ウェル領域（２５）をソース電極（
３２）に接続すると共に、ウェル領域（２５）の底部に
高濃度埋込層（３３）を設けることにより、アバランシ
ェ耐量を増大した縦型ＭＯ５ＦＥＴを提供するへのであ
る。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks of the conventional art.
A P-type well region (25) is provided to surround the P-type diffusion region (24) of the cell, and the well region (25) is connected to the source electrode (
32) and by providing a heavily doped buried layer (33) at the bottom of the well region (25), a vertical MO5FET with increased avalanche resistance is provided.
（ネ）作用
本発明によれば、高濃度埋込層（３３）を設けたことに
より基板（２１〉周囲部分において空乏層（３４）の伸
びが抑制され、その内部電界が部分的に高くなるので、
ＭＯＳセル内部のアバランシェ降伏電圧より周囲のアバ
ランシェ降伏電圧を小さくできる。すると、アバランシ
ェ降伏は先ず基板（２１）周囲部分で発生し、その降伏
電流は、ウェル領域〈２５）を介してソース電極（３２
）に流れる。ウェル領域（２５）はＰ型拡散領域（２４
）と分離形成されているので、前記降伏電流ｉがＭＯＳ
セル内で寄生トランジスタを導通させることが無く、さ
らにウェル領域（２５）にはＮ“型ソース領域（２９）
が存在しないので、ウェル領域（２５）で寄生トランジ
スタ効果が生じることも無い。従って、アバランシェ降
伏を流ｉを積極的にウェル領域（２５）へ流すことによ
って、ＭＯＳセル部の破壊を防止できる。(f) Effect According to the present invention, by providing the highly doped buried layer (33), the extension of the depletion layer (34) in the surrounding area of the substrate (21) is suppressed, and the internal electric field becomes locally high. So,
The surrounding avalanche breakdown voltage can be made smaller than the avalanche breakdown voltage inside the MOS cell. Then, avalanche breakdown first occurs around the substrate (21), and the breakdown current flows through the well region (25) to the source electrode (32).
). The well region (25) is a P-type diffusion region (24
), the breakdown current i is formed separately from the MOS
There is no parasitic transistor conduction within the cell, and the well region (25) is provided with an N" type source region (29).
Since there is no parasitic transistor effect in the well region (25). Therefore, by actively flowing the avalanche breakdown current i into the well region (25), destruction of the MOS cell portion can be prevented.
（へ）実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。第１図と第２図は夫々本発明の縦型ＭＯ３ＦＥ
Ｔを示す断面図と平面図であるゆ共通ドレインとなるシ
リコン半導体基体（２１）は、裏面電極形成用のＮ“型
半導体層（２２）と、Ｎ−型エピタキシヤル層（２３）
との２層構造から成る。(F) Example An example of the present invention will be described below in detail with reference to the drawings. Figures 1 and 2 are vertical MO3FE of the present invention, respectively.
A cross-sectional view and a plan view showing T are a silicon semiconductor substrate (21) that becomes a common drain, an N" type semiconductor layer (22) for forming a back electrode, and an N- type epitaxial layer (23).
It consists of a two-layer structure.
エピタキシヤル層（２３）の表面には、Ｐ型拡散領域（
２４）が形成され、その周囲を取り囲むようにしてＰ型
のウェル領域（２５）が形成されている。ウェル領域（
２５）の周囲には、これをさらに取り囲むようにＰ型の
ガードリング（２６〉が幾重にも形成される。（２７）
はＮ０型チヤンネルストツパ、（２８）はフィールド電
極である。On the surface of the epitaxial layer (23), there is a P-type diffusion region (
24) is formed, and a P-type well region (25) is formed surrounding it. Well area (
Around 25), P-type guard rings (26>) are formed in multiple layers to further surround this. (27)
is an N0 type channel stopper, and (28) is a field electrode.
Ｐ型拡散領域（２４）の表面には、Ｎゝ型ソース領域（
２９）が形成され、ソース領域（２９）とエピタキシャ
ル層（２３）表面で挾まれたＰ型拡散領域〈２４）の表
面をチャンネル部とする。チャンネル部上には、シリコ
ン酸化膜から成るゲート絶縁膜（３０〉を介してポリシ
リコンのゲート電極（３１）が配置されている。尚、縦
型ＭＯ５ＦＥＴのパターンには、Ｐ型拡散領域（２４）
が点在しゲート電極（３１）が格子状になるメツシュゲ
ート型と、Ｐ型拡散領域（２４〉が格子状になりゲート
電極（３１）が格子部分に点在するマルチゲート型との
２種類があり、第２図はマルチゲート型のパターンを示
している。On the surface of the P-type diffusion region (24), an N-type source region (
29) is formed, and the surface of the P-type diffusion region (24) sandwiched between the source region (29) and the surface of the epitaxial layer (23) is used as a channel portion. A polysilicon gate electrode (31) is arranged on the channel part with a gate insulating film (30) made of a silicon oxide film interposed therebetween.The pattern of the vertical MO5FET includes a P-type diffusion region (24). )
There are two types: a mesh gate type in which the gate electrodes (31) are dotted in a lattice shape, and a multi-gate type in which the P-type diffusion regions (24> are in a lattice shape and the gate electrodes (31) are dotted in the lattice part). 2 shows a multi-gate pattern.
ウェル領域（２５）の表面にはソース領域（２９）も何
も設けない。これで、Ｐ型ウェル領域（２５）はＭＯＳ
セルとして動作できないブローティングの状態となる。No source region (29) is provided on the surface of the well region (25). Now, the P-type well region (25) is a MOS
It enters a bloating state where it cannot operate as a cell.
マルチゲート型の場合、個々に独立したゲート電極（３
１〉は、櫛歯状のアルミ電極によって共通接続され外部
接続用の図示せぬポンディングパッドに接続されている
。Ｐ型拡散領域（２４）の表面には、Ｐ型拡散領域（２
４）とソース領域（２９）の両方にコンタクトするソー
ス電極（３２）が櫛歯状に形成されて図示せぬソースポ
ンディングパッドに接続されている。In the case of a multi-gate type, each independent gate electrode (3
1> are commonly connected by a comb-shaped aluminum electrode and connected to a not-shown bonding pad for external connection. On the surface of the P-type diffusion region (24), there is a P-type diffusion region (24).
A source electrode (32) in contact with both the source region (29) and the source region (29) is formed in a comb-like shape and is connected to a source bonding pad (not shown).
高濃度埋込層（３３）は、基体（２１）のＮ”型半導体
層（２２）とＮ−型エピタキシャル層（２３）との境界
部分に設けられ、その境界から上下に一定厚みだけ拡散
形成されている。また、高濃度埋込Ｈ（３３）は、ＭＯ
Ｓセル部分を除き、少くともＰ型ウェル領域（２５）の
底部に位置するように選択的に設けられる。その埋込層
（３３）は、先ずＮ１型半導体層（２２）をウェハとし
、この表面にアンチモン（Ｓｂ）を選択的にデポジット
し、ウェハ上に所望厚みのエピタキシャル層（２３）を
エピタキシャル成長することで得られる。不純物濃度は
エピタキシャル層（２３〉より高いものとする。The high concentration buried layer (33) is provided at the boundary between the N'' type semiconductor layer (22) and the N- type epitaxial layer (23) of the base body (21), and is formed by diffusion to a certain thickness above and below the boundary. In addition, the high concentration embedded H (33) is MO
Except for the S cell portion, it is selectively provided so as to be located at least at the bottom of the P-type well region (25). The buried layer (33) is first formed by using the N1 type semiconductor layer (22) as a wafer, selectively depositing antimony (Sb) on the surface of the wafer, and epitaxially growing an epitaxial layer (23) with a desired thickness on the wafer. It can be obtained with The impurity concentration is higher than that of the epitaxial layer (23).
高濃度埋込層（３３）が上方向に拡散された結果、Ｐ型
ウェル領域（２５）底部におけるエピタキシャル層（２
３）の実質的な厚みｔ、は、ＭＯＳセル部のＰ型拡散領
域（２４）底部におけるエピタキシャル層（２３）の実
施的な厚みｔ、より小さくなる。従って、ウェル領域（
２５）の底部では空乏層（３４）の伸びが高濃度埋込層
（３３）に阻止されることになる。As a result of the upward diffusion of the heavily doped buried layer (33), the epitaxial layer (2) at the bottom of the P-type well region (25)
The substantial thickness t of 3) is smaller than the actual thickness t of the epitaxial layer (23) at the bottom of the P-type diffusion region (24) in the MOS cell portion. Therefore, the well area (
At the bottom of 25), the expansion of the depletion layer (34) is blocked by the highly doped buried layer (33).
断る構成の縦型ＭＯＳＦＥＴにおいて、ソース・ドレイ
ン間にリアクトル負荷の逆起電力によって逆方向電圧が
印加された場合、高濃度埋込層（３３）によって空乏層
（３４）の伸びが抑制されるので、素子のアバランシェ
降伏はＭＯＳセル部より先に埋込層〈３３）を設けた部
分で発生し、その降伏電流は、ウェル領域（２５）にソ
ース電極（３２）がコンタクトしているので、ウェル領
域（２５）を介してソース電極（３２）に流れる。ウェ
ル領域〈２５）には寄生トランジスタが存在しないので
、この部分でラッチアップが生じるはずも無く、且つウ
ェル領域（２５）とＰ型拡散領域〈２４）とは分離され
ているの１で、ウェル領域（２５）に流れたアバランシ
ェ電流がＭＯＳ部分でラッチアップさせることも無い。In a vertical MOSFET with a negative configuration, when a reverse voltage is applied between the source and drain due to the back electromotive force of the reactor load, the highly doped buried layer (33) suppresses the expansion of the depletion layer (34). , the avalanche breakdown of the device occurs in the part where the buried layer (33) is provided before the MOS cell part, and the breakdown current occurs in the well region (25) because the source electrode (32) is in contact with it. It flows through the region (25) to the source electrode (32). Since there is no parasitic transistor in the well region (25), latch-up cannot occur in this part, and since the well region (25) and the P-type diffusion region (24) are separated1, The avalanche current flowing in the region (25) does not cause latch-up in the MOS portion.
従って、ＭＯＳセル部分において寄生トランジスタを導
通させることが無いので、素子を破壊から保護できる。Therefore, since the parasitic transistor is not made conductive in the MOS cell portion, the element can be protected from destruction.
（ト）発明の効果
以上に説明した通り、本発明によれば高濃度埋込層（３
３）を形成することによって、アバランシェ電流を積極
的にウェル領域（２５）に流すので、ＭＯＳセルの寄生
トランジスタを導通させることが無く、従って素子を破
壊から保護することができる利点を有する。(g) Effects of the invention As explained above, according to the present invention, the high concentration buried layer (3
By forming 3), an avalanche current is actively caused to flow in the well region (25), so that the parasitic transistor of the MOS cell is not made conductive, which has the advantage that the device can be protected from destruction.
第１図と第２図は夫々本発明を説明するための断面図と
平面図、第３図〜第５図は夫々従来例を説明するための
断面図、回路図、拡大断面図である。1 and 2 are a sectional view and a plan view, respectively, for explaining the present invention, and FIGS. 3 to 5 are a sectional view, a circuit diagram, and an enlarged sectional view, respectively, for explaining a conventional example.
Claims (2)
ャル層と、 前記エピタキシャル層表面のＭＯＳ素子形成用領域に形
成した逆導電型の半導体領域と、 前記半導体領域の表面に形成した一導電型のソース領域
と、 チャンネル部上に絶縁膜を介して配置したゲート電極と
、 前記エピタキシャル層表面のＭＯＳ素子形成用領域を囲
む領域に形成した逆導電型のウェル領域と、 前記ウェル領域の更に外側を囲む逆導電型のガードリン
グ領域と、 前記ウェル領域下部の前記半導体基板表面に設けた前記
エピタキシャル層よりは高不純物濃度の一導電型埋込層
と、 前記ソース領域および前記ウェル領域にコンタクトする
ソース電極とを具備し、 前記半導体基板の表面から前記逆導電型領域底部までの
エピタキシャル層の実質的な厚みより、前記埋込層の表
面から前記ウェル領域底部までのエピタキシャル層の実
質的な厚みを小さくしたことを特徴とする縦型ＭＯＳＦ
ＥＴ。(1) An epitaxial layer formed on the surface of a semiconductor substrate of one conductivity type, a semiconductor region of the opposite conductivity type formed in a MOS element formation region on the surface of the epitaxial layer, and a semiconductor region of one conductivity type formed on the surface of the semiconductor region. a source region, a gate electrode disposed on the channel portion with an insulating film interposed therebetween, a well region of an opposite conductivity type formed in a region surrounding the MOS element formation region on the surface of the epitaxial layer, and further outside the well region. a guard ring region of opposite conductivity type surrounding the semiconductor substrate; a buried layer of one conductivity type with a higher impurity concentration than the epitaxial layer provided on the surface of the semiconductor substrate below the well region; and a source contacting the source region and the well region. an electrode, the substantial thickness of the epitaxial layer from the surface of the buried layer to the bottom of the well region is greater than the substantial thickness of the epitaxial layer from the surface of the semiconductor substrate to the bottom of the opposite conductivity type region. Vertical MOSF characterized by its small size
E.T.
の表面に格子状に設けられその周囲を囲むように前記ウ
ェル領域が前記逆導電型拡散領域とは分離して設けられ
ていることを特徴とする請求項第１項に記載の縦型ＭＯ
ＳＦＥＴ。(2) The diffusion region of the opposite conductivity type is provided in a grid pattern on the surface of the epitaxial layer, and the well region is provided separately from the diffusion region of the opposite conductivity type so as to surround the diffusion region. The vertical MO according to claim 1,
SFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1295931A JPH0793436B2 (en) | 1989-11-14 | 1989-11-14 | Vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1295931A JPH0793436B2 (en) | 1989-11-14 | 1989-11-14 | Vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03155678A true JPH03155678A (en) | 1991-07-03 |
| JPH0793436B2 JPH0793436B2 (en) | 1995-10-09 |
Family
ID=17826973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1295931A Expired - Fee Related JPH0793436B2 (en) | 1989-11-14 | 1989-11-14 | Vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793436B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007096344A (en) * | 1998-11-11 | 2007-04-12 | Fuji Electric Device Technology Co Ltd | Superjunction semiconductor device manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59149058A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Works Ltd | Metal oxide semiconductor type transistor |
| JPS6319844A (en) * | 1986-07-14 | 1988-01-27 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS63138779A (en) * | 1986-11-29 | 1988-06-10 | Nec Kansai Ltd | Semiconductor element |
-
1989
- 1989-11-14 JP JP1295931A patent/JPH0793436B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59149058A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Works Ltd | Metal oxide semiconductor type transistor |
| JPS6319844A (en) * | 1986-07-14 | 1988-01-27 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS63138779A (en) * | 1986-11-29 | 1988-06-10 | Nec Kansai Ltd | Semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007096344A (en) * | 1998-11-11 | 2007-04-12 | Fuji Electric Device Technology Co Ltd | Superjunction semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793436B2 (en) | 1995-10-09 |
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