JPH03160761A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short channel effect without lowering switching speed by constituting a first gate electrode and a second gate electrode of the materials having mutually different work functions. CONSTITUTION:A first gate electrode 6a is faced to a channel having the length L1 of both sides of a groove through a gate insulating film 5 so as to constitute an equivalent transistor P. Further, a second gate electrode 6b is faced to a channel having the length L2 of the base of the groove through the same gate insulating film 5 so as to form an equivalent transistor Q. Accordingly, an equivalent circuit of the device come to be expressed by that where these equivalent transistors P and Q are in series connected, in this case, by forming the first and second gate electrodes 6a, 6b of the materials having the mutually different work functions, threshold value voltage of the equivalent transistors P and Q can be made different. Thereby, a short channel effect can be prevented without lowering switching speed.

Description

[Detailed Description of the Invention] [Summary] Regarding the structure of a MOSh transistor, the purpose is to prevent the short channel effect without reducing the switching speed. a shaped layer of opposite conductivity type, a groove penetrating the layer of opposite conductivity to reach the semiconductor substrate of one conductivity type, a gate insulating film shaped on the inner surface of the groove, and a gate insulating film formed on the inner surface of the groove; A semiconductor device comprising: a first gate electrode formed on a side surface of the trench; and a second gate electrode formed on a bottom surface of the trench with the gate insulating film interposed therebetween; The electrode and the second gate electrode are made of materials having different work functions, or
Alternatively, the first gate electrode is made of polycrystalline silicon of one conductivity type, and the second gate electrode is made of polycrystalline silicon of the opposite conductivity type.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to the structure of a MOS transistor.

In order to increase the density of MOS transistors by improving switching speed and reducing the area occupied by the elements,
First of all, miniaturization of the channel length is required.

However, in a normal MOS transistor structure, as the channel length is shortened, impurities in the source/drain region begin to wrap around the channel region under the gate electrode, causing fluctuations in the threshold voltage and bunch-through phenomenon. This causes a so-called short channel effect, such as short channel effect, and deteriorates transistor characteristics. This short channel effect is a major cause of hindering the reduction of the channel length of MOS transistors, and a solution to this problem is desired.

[Prior art] In order to prevent the above-mentioned short channel effect,
Hitherto, a buried transistor as shown in FIG. 3 has been proposed. In the figure, after forming an n'' layer 3 and an n-layer 4, which will become source/drain regions, using an ion implantation method on a p-type silicon substrate 1 having an insulating film 2 for element isolation, an n' layer 3 and an n-i layer 4 are formed. A groove is formed by selective etching that penetrates the substrate and reaches the p-type silicon substrate 1. Then, a gate insulating film 5 is formed on the inner surface of the substrate, and n-type polycrystalline silicon is buried in the groove to form a gate electrode 6. .Furthermore, after forming the PSG film 7 on the entire surface by CVD method,
Source/drain electrodes 8a and 8 are formed by opening windows on the layer 3.
form b.

As described above, in a buried transistor, by shaping the trench, it is possible to reduce the amount of impurities from entering the channel region from the n layer 3 and the n layer 4, thereby preventing the short channel effect. There are problems as described in . That is, as shown in FIG.
The etching depth of the groove formed in is L1, and the width of the groove is L2.
Then, the channel length is expressed as 2L+ +L, which is 2L longer than a normal MOS transistor without grooves. Moreover, the etching depth L1 of the groove must be increased in order to reliably prevent the short channel effect. This makes the channel length longer than necessary, resulting in a significant reduction in switching speed.

In order to eliminate the above-mentioned drawbacks, an improved buried transistor as shown in FIG. 4(a) has been proposed. In this figure, the same parts as in FIG. 3 are given the same numbers.

In the buried transistor shown in the figure, boron (B) ions are implanted over the entire surface after forming the trench, and p
A P-type channel doped region 9 having a higher impurity concentration than that of the type-1 silicon substrate 1 is formed. In the above ion implantation, the boron implanted into the n'' layer 3 is canceled out by the impurity in the n'' layer 3, and is not implanted into the side surfaces of the trench. Therefore, the equivalent circuit of this improved buried transistor is as follows: The same figure (b
), the channel length L1 on both sides of the groove
The equivalent transistor P,? On the bottom surface of M, equivalent transistors Q having a channel length L2 are connected in series with a common gate electrode 6.

Incidentally, it is known that the threshold voltage of a MOS transistor generally changes depending on the work function difference Φ1 between the gate electrode and the channel region.

In the above improved embedded transistor, the equivalent transistor P
Since the impurity concentrations of the channel regions of and Q are different, each Φ8 is also different, and as a result, each threshold voltage takes a different value. Therefore, by applying an appropriate substrate bias, the equivalent transistor P has a negative threshold voltage to operate in depletion mode, and the equivalent transistor Q has a positive threshold voltage to operate in enhancement mode. You can make it work. In this way, the equivalent transistor P always operates in the on state, and only the equivalent transistor Q performs the switching operation, and the switching speed of the improved embedded transistor is substantially the same as that of the equivalent transistor Q.
It is determined only by the characteristics of Since the channel length of the equivalent transistor Q is equal to the trench width L2, the effective channel length is shorter than the channel length 2L++Lz of the buried transistor shown in FIG.

(Problem to be Solved by the Invention! gi) However, in the above-mentioned improved embedded transistor, the operating current range is limited by the on-current of the equivalent transistor P operating in depletion mode. In order to widen this operating current range, it is necessary to make the difference between the threshold voltages of the equivalent transistors P and Q as large as possible, and for this purpose, the impurity concentration of the p-type Char impurity doped region 9 must be increased to p- It is necessary to make the impurity concentration sufficiently higher than the impurity concentration of the type silicon substrate l. However, in the channel doped region 9 with a high impurity concentration, the electric field in the depletion layer becomes strong, the mobility of carriers decreases, and the switching speed also decreases.

Therefore, an object of the present invention is to prevent the short channel effect without reducing the switching speed.

(Means for Solving the Problem) The solution to the above problem is to provide a semiconductor substrate of one conductivity type, a layer of an opposite conductivity type formed on the semiconductor substrate of one conductivity type, and a layer of opposite conductivity type formed on the semiconductor substrate of one conductivity type, and a layer of opposite conductivity type formed on the semiconductor substrate of one conductivity type. a groove reaching one conductivity type semiconductor substrate; a gate insulating film formed on the inner surface of the groove; a first gate electrode formed on the side surface of the groove via the gate insulating film;
A semiconductor device having a second gate electrode formed on the bottom surface of the trench via the gate insulating film, the first gate electrode and the second gate electrode having different work functions from each other. or the semiconductor device characterized in that the first gate electrode is made of one conductivity type polycrystalline silicon and the second gate electrode is made of opposite conductivity type polycrystalline silicon. achieved by

[Function] FIGS. 1(a) and (b) are explanatory diagrams of the principle of the semiconductor device according to the present invention, and parts having the same functions as those in FIGS. 4(a) and (b) are designated by the same numbers. Attached. As seen in the figure, for a channel of length L1 on both sides of the groove,
A first gate electrode 6a faces each other with a gate insulating film 5 interposed therebetween, and constitutes an equivalent transistor P. Also,
A second gate electrode 6b faces the channel having a length L2 at the bottom of the trench with the same gate insulating film 5 interposed therebetween, and this gate electrode 6b faces the equivalent transistor Q. From the above, the equivalent circuit of the semiconductor device according to the present invention is represented by the equivalent transistors P and Q connected in series, as shown in FIG.
By forming the first and second gate electrodes 6a, 6b with materials having different work functions, it is possible to make the threshold voltages of the equivalent transistors P and Q different. That is, in the buried transistor shown in FIG. 4, the difference in threshold voltage between the equivalent transistors P and Q is created by providing the channel doped region 9, whereas in the present invention, the difference in threshold voltage between the equivalent transistors P and Q is created by providing the channel doped region 9. a gate electrode 6a having a different work function,
6b is used to create a difference in threshold voltage. In the structure of the present invention, by appropriately selecting the gate electrode material, the threshold voltages of the equivalent transistors P and Q can be controlled over a wide range without providing a channel tobe region.

In particular, when each of the first and second gate electrodes 6a, 6b is formed of polycrystalline silicon of one conductivity type and polycrystalline silicon of opposite conductivity type, which have different work functions, by applying an appropriate substrate bias, the equivalent transistor P
can be operated in depletion mode and the equivalent transistor Q can be operated in enhancement mode. In this case, it becomes possible to keep the equivalent transistor P always in the on state and switch only the equivalent transistor Q, and as a result, the effective channel length is 2L.
．． +L2 is shortened from +L2 to L2, and since there is no need to increase the impurity concentration in the channel region unlike the conventional buried transistor shown in FIG. 4, the switching speed does not decrease.

[Example] Hereinafter, an example of the present invention will be described with reference to a sectional view of a scale shown in FIG.

First, as shown in Figure (a), oxidation 1 and 2 for element isolation
An accelerating voltage of 70κeν and a torse amount of 4
Arsenic (As) ions were implanted under the condition of IOl 5 cm-'' to form the n layer 3, followed by an accelerating voltage of 50 KeV,
Dawes view I
) Serves as Aeon's master and prescribes n-layer 4. Under the above ion implantation conditions, P ions are implanted deeper than As ions, and as a result, the n- layer 4 becomes the n-layer 3 as shown in the figure.
will be formed below. After that, the full 500 yen passes through the n' layer 3 and the n- layer 4 and reaches the p-type silicon substrate 1.
A is formed by selective etching, and then the entire surface is thermally oxidized to form a gate oxide film 5 on the inner surface of the groove 58. Next, apply boron (B) to the entire surface at a degree I XIO"cm-'
A type polycrystalline silicon is deposited by the CVD method and anisotropically etched, leaving only the sidewalls of the silicon layer as the first gate electrode 6a, as shown in FIG. 6(b). Then p
N-type polycrystalline silicon of 4 degrees I This is used as the second gate electrode 6b.

Thereafter, according to the usual process, as shown in 1](a), after depositing PSC; Drain electrodes 8a and 8b are formed.

In the above embodiment, Φ9 of the equivalent transistor P constituted by the first gate electrode 6a is -0.7V, and the second
Φ of the equivalent transistor Q constituted by the gate pole 6b. becomes 0.3V. Therefore, by applying an appropriate substrate bias, the equivalent transistor P is always turned on, and only the equivalent transistor Q is operated for switching, thereby shortening the effective channel length and improving the switching speed.

Contrary to the above embodiment, the equivalent transistor Q
It is also possible to always keep the transistor in the on state and only the equivalent transistor P performs the switching operation. In this case, the equivalent transistor P determines the overall switching speed.

Further, as a matter of course, the materials used for the first and second gate electrodes are not limited to polycrystalline silicon, but metals having different work functions can also be used.

(Effects of the Invention) As described above, according to the present invention, it is possible to prevent the short channel effect without reducing the switching speed, so it is possible to reduce the area occupied by the MOS transistor, and to increase the density of the IC. It has a great effect on speed and speed.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are diagrams explaining the principle of the present invention, and Figure 2 (
a) to (C) are process sectional views of the present invention, and FIGS. 3 and 4 are diagrams showing problems in the conventional example. In the figure, 1 is a p-type silicon substrate, 2 is an insulating film for element isolation, 3 is an n9 layer, 4 is an n-layer, 5 is a gate insulating film, 5a is a groove, 6 is a gate electrode, 6a is a first gate Electrodes, 6b is the second gate electrode, 7 is the PSG film, 8a and 8b are the source/train electrodes, 9 is the p-type channel doped region, *Shimei's principle explanatory diagram 1! lIT surface diagram

Claims (1)

[Scope of Claims] [1] A semiconductor substrate (1) of one conductivity type, layers (3, 4) of opposite conductivity type formed on the semiconductor substrate (1) of one conductivity type, and layers (3, 4) of opposite conductivity type formed on the semiconductor substrate (1) of one conductivity type. 3, 4) reaching the one conductivity type semiconductor substrate (1); a gate insulating film (5) formed on the inner surface of the trench; and a trench extending through the gate insulating film (5). A semiconductor device comprising: a first gate electrode (6a) formed on a side surface of the groove; and a second gate electrode (6b) formed on the bottom surface of the trench with the gate insulating film (5) interposed therebetween. , the first gate electrode (6a) and the second gate electrode (6a).
A semiconductor device characterized in that b) is made of materials having mutually different work functions. [2] Claim [1] characterized in that the first gate electrode (6a) is made of polycrystalline silicon of one conductivity type, and the second gate electrode (6b) is made of polycrystalline silicon of the opposite conductivity type.
The semiconductor device described.