JPH04346272A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the drive capacity by reducing the depth of a well region in a channel section smaller than the width of a gate depletion layer to which the width of well-to-well board depletion layer is added compared with the depth of a well region in a diffusion layer section of a source or a drain. CONSTITUTION:The depth Xj1 of a first well region 2-1 is arranged to establish the relation of Xj1<Wg+Ws, assuming that the width of a channel depletion layer formed by the voltage applied to a gate electrode 6 is Ws. The depth Xj2 of a second well region 2-2 is arranged to hold the relation of Xj2>Wd+ Ws, assuming that the width of a depletion layer formed by a source region 3 and a drain region 4 is Wd. Due to this relation, the charge of the depletion layer of MOSEFT are fluctuated by the voltage Vsub of the silicon board. More specifically, the depletion charges are reduced by raising the voltage Vsub.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a semiconductor device of MOS type structure and a method of manufacturing the same.

0002

2. Description of the Related Art FIG. 5 is a sectional view showing the structure of a conventional semiconductor device, an N-channel type MOS FET. A gate oxide film 12 is formed on a P-type silicon substrate 11, and a gate electrode 13 is connected to the gate oxide film 12. N+ type source region 14 and drain region 15 are formed on the surface of substrate 11 with gate oxide film 12 in between.

In the MOS FET having the above structure, a depletion layer is formed in the channel when a gate bias is applied. Since the depletion layer charges in this depletion layer strengthen the effective gate electric field, carrier mobility decreases. Also, the gate electric field applied in the inversion layer is reduced, and the carrier concentration is reduced. Therefore, the driving ability of the MOS FET will be reduced. Furthermore, there is also the problem of the so-called back gate bias effect, in which the threshold value increases when a substrate bias is applied.

0004

[Problems to be Solved by the Invention] Conventionally, the capacitance of each depletion layer charge in the gate, source, and drain of a MOS FET has an adverse effect on improving the performance of the MOS FET, leading to a decrease in the MOS driving ability. It has the disadvantage of causing

The present invention has been made in consideration of the above-mentioned circumstances, and its object is to provide a high-performance MOS structure semiconductor device with high driving capability and a method for manufacturing the same.

[0006]

[Means for Solving the Problems] A semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, a gate electrode formed on the substrate with a thin insulating film interposed therebetween, and a gate electrode formed from below the edge of the gate electrode. a first conductivity type diffusion region formed on the substrate surface so as to extend further away from the gate electrode; and a channel depletion formed by a voltage applied to the gate electrode in a channel region portion of the semiconductor substrate below the gate electrode. a second conductivity type formed in a channel region of the semiconductor substrate below the gate electrode and having a PN junction depth smaller than the sum of the layer width and the depletion layer width formed by the substrate voltage of the semiconductor substrate; the first semiconductor region, the depletion layer width formed in the diffusion region portion, and the first semiconductor region formed by the substrate voltage of the semiconductor substrate;
A second conductive type second conductive layer formed in the diffusion layer region so as to extend into the first semiconductor region and having a PN junction depth greater than the sum of the depletion layer width within the semiconductor region. It is characterized by comprising a semiconductor region.

The method for manufacturing a semiconductor device according to the present invention includes a first method for manufacturing a semiconductor device.
a step of forming a first well region of a second conductivity type on a surface of a semiconductor substrate of a conductivity type; a step of forming a thin insulating film on the substrate; a step of forming a gate electrode on the insulating film;
A step of introducing an impurity of a first conductivity type into the surface of the substrate using the gate electrode as a mask to form a diffusion region, and a step of introducing an impurity of a second conductivity type using the gate electrode as a mask to surround the diffusion region. A second conductivity type second well region is connected to the first conductivity type second well region.
The method is characterized by comprising a step of forming the well region so as to extend into the well region.

[0008]

In the present invention, the depth of the well region is different between the channel region and the diffusion region below the gate electrode. For example, it is deep in the source and drain diffusion layers and shallow in the channel region. Moreover, the depth of the well region in the channel portion is made shallower than the sum of the gate depletion layer width and the well-substrate depletion layer width. Furthermore, the concentration is lower than that of the diffusion layer portion. This allows the MOS
Suppresses FET depletion layer charge.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described by way of embodiments with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an N-channel type MOS FET according to an embodiment of the present invention. P-type first and second well regions 2-1 and 2-2 are formed on the surface of an N-type silicon substrate 1. The first well region 2-1 is formed along the channel region. The second well region 2-2 extends from the first well region 2-1 and is formed to surround the N+ type source region 3 and drain region 4. These well regions 2-1
, 2-2, a gate oxide film 5 is formed, and a gate electrode 6 is formed on the gate oxide film 5 with a source region 3 and a drain region 4 separated therebetween.

Depth Xj1 of the first well region 2-1
When Wg is the width of the channel depletion layer formed by the voltage applied to the gate electrode 6 and Ws is the width of the depletion layer formed by the substrate voltage of the silicon substrate 1, the following relationship holds true. . Xj1<Wg+Ws...(1)

Depth Xj of the second well region 2-2
2 is such that the following relationship holds true, where Wd is the width of the depletion layer formed by the source region 3 and drain region 4, and Ws is the width of the depletion layer formed by the substrate voltage of the silicon substrate 1. Xj2>Wd+Ws…(2)

According to the above embodiment, the depth Xj1 of the first well region 2-1 formed in the channel region is
) This MOS FET
The depletion layer charge of the channel of is equal to the voltage Vs of the silicon substrate 1
It varies depending on ub. That is, by increasing the voltage Vsub, the charge in the channel depletion layer is reduced. Furthermore, the depth Xj2 of the second well region 2-2 has the relationship shown in equation (2) above, and the configuration is such that punch-through does not occur between the source and drain regions 3 and 4 and the silicon substrate 1. It has become.

[0014] Therefore, M. Yoshimi, T. Wad
a, K. Kato, and H. Tango, TEDM
Tech. Dig. ,P. 640 (1987)
T and T. Mizuno, T. Higuchi, Y.
Saitoh, S. Sawada, and S. Shi
nozaki, Symp. VLSI Tech. Dig
．． ,P. 23 (1988)
High driving ability, S- due to the same mechanism as S
It is expected that the swing will be improved and the substrate bias effect will be reduced while obtaining the desired value of the threshold voltage Vth. An example of a method for manufacturing the MOS FET having the above configuration is shown below.

As shown in FIG. 2, B+ ions are implanted into the surface of an N-type silicon substrate 1 to a depth of about 500 nm.
, a P-type first well region 2-1 with an impurity concentration of 1×10 17 cm −3 is formed. Next, a 15 nm film was deposited on substrate 1.
A gate oxide film 5 is formed, and a gate electrode 6 is formed on the gate oxide film 5.

Thereafter, As+ is ion-implanted using the gate electrode 6 as a mask to form diffusion regions 3 and 4 with an impurity concentration of 1×10 20 cm −3 as sources and drains. Furthermore, B+ ions are implanted at high energy using the gate electrode 6 as a mask, and the impurity concentration is 1×1 so as to extend into the first well region 2-1 and surround the diffusion regions 3 and 4.
A second well region 2-2 of 018 cm-3 is formed (
Figure 1).

FIG. 3 shows another embodiment of the structure of a MOS type semiconductor device in which the drain region 4 is not formed compared to FIG. The source region 3 is grounded, and the substrate 1 side is used as a drain by applying a substrate bias. The method of operation is to inject electrons from the inversion layer in the channel region into the substrate. Since only one side of the source region 3 is provided as the diffusion region,
Even if the gate becomes smaller and the channel length becomes shorter, transistor operation without short channel effects is possible.

FIG. 4 is a sectional view showing an example of application of FIG. 3. A transistor having the structure of FIG. 3 is formed adjacent to field oxide film 7. The operating method is the same as in FIG. With the source region 4 grounded and the substrate bias Vsub applied, a transistor is constructed which conducts in the vertical direction in the figure as indicated by the broken arrow 8 with the substrate 1 side as the drain.

In each of the above embodiments, an N-channel type semiconductor device is shown, but the silicon substrate 1 is of P type, the first
Even if a P-channel type semiconductor device is constructed in which the second well regions 2-1 and 2-2 are of N type and the source region 3 and drain region 4 are of P+ type, the same effects as in the embodiment can be expected. .

[0020]

[Effects of the Invention] As explained above, according to the present invention,
Compared to the depth of the well region in the source and drain diffusion layer parts, the depth of the well region in the channel part is made shallower than the sum of the gate depletion layer width and the depletion layer width between the well and the substrate, resulting in high drive. A semiconductor device having a high performance MOS structure and a method for manufacturing the same can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a configuration according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of the process of manufacturing the configuration shown in FIG. 1;

FIG. 3 is a sectional view of a configuration according to another embodiment of the invention.

FIG. 4 is a cross-sectional view of a configuration showing an application example of FIG. 3;

FIG. 5 is a cross-sectional view showing the configuration of a conventional semiconductor device.

[Explanation of symbols]

1... Silicon substrate, 2-1... First well region, 2-
2... Second well region, 3... Source region, 4... Drain region, 5... Gate oxide film, 6... Gate electrode.

Claims (6)

[Claims] 1. A semiconductor substrate of a first conductivity type, a gate electrode formed on the substrate with a thin insulating film interposed therebetween, and a surface of the substrate extending from below an edge of the gate electrode to a distance from the gate electrode. A channel depletion layer width formed by a voltage applied to the gate electrode in a channel region portion of the semiconductor substrate below the gate electrode and a substrate voltage of the semiconductor substrate. a first semiconductor region of a second conductivity type formed in a channel region of the semiconductor substrate below the gate electrode and having a PN junction depth smaller than the sum of the depletion layer width and the diffusion region portion; The first semiconductor region has a PN junction depth greater than the sum of the depletion layer width formed in the semiconductor substrate and the depletion layer width in the first semiconductor region formed by the substrate voltage of the semiconductor substrate. a second semiconductor region of a second conductivity type formed in the diffusion layer region so as to extend into the diffusion layer region. 2. The semiconductor device according to claim 1, wherein the operating mode is a current flow in a vertical direction from the diffusion region toward the semiconductor substrate below the gate electrode. 3. The method according to claim 1, wherein the current flow is in a lateral direction from the diffusion region through a channel region below the gate electrode to under the edge of the gate electrode on the opposite side. Semiconductor equipment. 4. Forming a first well region of a second conductivity type on the surface of a semiconductor substrate of a first conductivity type, forming a thin insulating film on the substrate, and forming a gate electrode on the insulating film. a step of introducing an impurity of a first conductivity type into the surface of the substrate using the gate electrode as a mask to form a diffusion region; a step of introducing an impurity of a second conductivity type using the gate electrode as a mask; a second conductivity type surrounding the diffusion region;
A method of manufacturing a semiconductor device, comprising the step of forming a well region so as to extend into the first well region. 5. The first well region is formed by a channel depletion layer width formed by a voltage applied to the gate electrode in a channel region portion of the semiconductor substrate below the gate electrode and a substrate voltage of the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the PN junction depth is smaller than the sum of the depletion layer width and the depletion layer width. 6. The second well region is larger than the sum of the depletion layer width formed in the diffusion region portion and the depletion layer width in the first semiconductor region formed by the substrate voltage of the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed to have a depth of a PN junction.