JPH0316218A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0316218A
JPH0316218A JP15186689A JP15186689A JPH0316218A JP H0316218 A JPH0316218 A JP H0316218A JP 15186689 A JP15186689 A JP 15186689A JP 15186689 A JP15186689 A JP 15186689A JP H0316218 A JPH0316218 A JP H0316218A
Authority
JP
Japan
Prior art keywords
electrode wiring
contact window
wiring layer
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15186689A
Other languages
Japanese (ja)
Inventor
Tomoyuki Sasaki
智幸 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15186689A priority Critical patent/JPH0316218A/en
Publication of JPH0316218A publication Critical patent/JPH0316218A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce electrode wiring resistance as well as prevent breakage by a method wherein electrically conductive resist is embedded on a first electrode wiring layer to be flattened on a contact window. CONSTITUTION:After an interlayer insulation film 13 is formed on a semiconductor substrate 11 and a contact window 14 is opened on a specific position by etching, a first aluminum electrode wiring layer 15 is adhered on a diffusion layer region 12 of the semiconductor substrate exposed at the contact window by deposition or the like. After electrically conductive resist 18 is adhered by spin application as a conductive organic high polymer compound on the layer 15, conductive resist except on a recess of the first aluminum electrode wiring layer 16 is removed by etch back to leave the conductive resist 18 only on the recess to be embedded and flattened. A second electrode wiring layer 13 is adhered on this. Thus flattening of the electrode layer of the contact window 14 can be done as well as electrode wiring resistance can be decreased thereby preventing breakage.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電極配線層と半導体基板中の拡散層のコンタ
クト部分での電極配線層の平坦化を図った半導体装置の
製造方法K関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device in which the electrode wiring layer is planarized at the contact portion between the electrode wiring layer and a diffusion layer in a semiconductor substrate. .

従来の技術 従来、第2図に示す様に半導体基板21の一主而上に層
間絶縁膜23としてBPSGを形戚し(b)、コンタク
ト窓24を開孔した後FC+、その上に蒸着等により第
1アルミ配線層25を形或しているf(11。
Conventionally, as shown in FIG. 2, BPSG is formed as an interlayer insulating film 23 on a semiconductor substrate 21 (b), and after a contact window 24 is opened, FC+ is deposited on it, etc. The first aluminum wiring layer 25 is formed by f(11).

発明が解決しようとする課題 従来、第2図に示す様に電極配線として使われているア
ルミ配線層は蒸着によう形威されるため、段差のあるコ
ンタクト窓では底部の中央部で厚くなる部分27と底部
の周辺部の角で薄くなる部分26とが存在する。その為
、電極配線抵抗が高くなったシ、時には周辺部の角で配
線が断線することも見られる。又、コンタクト窓付近で
半導体装置の段差が大きくなるなどの問題があった。
Problems to be Solved by the Invention Conventionally, as shown in Figure 2, the aluminum wiring layer used as electrode wiring is formed by vapor deposition, so in a contact window with a step, the part that becomes thick at the center of the bottom. 27 and a thinner portion 26 at the corner of the bottom periphery. As a result, the resistance of the electrode wiring increases, and sometimes the wiring breaks at the corners of the periphery. Further, there is a problem in that the level difference in the semiconductor device increases near the contact window.

本発明はかかる点に鑑み、コンタクト窓の電極配線抵抗
を低減することができる半導体装置の製造方法を提供せ
んとするものである。
In view of this point, the present invention seeks to provide a method for manufacturing a semiconductor device that can reduce the electrode wiring resistance of a contact window.

課題を解決するための手段 本発明は前記目的を達或するために、半導体基板上に層
間絶縁膜を被着する工程と、前記層間絶縁膜にコンタク
ト窓を開孔する工程と、前記コンタクト窓部分に露出し
た前記半導体基板の拡散層上に第1の電極配線層を被着
する工程と、コンタクト窓部分で前記第1の電極配線層
の凹部にスピン塗布及びエッチバックにより導電性の有
機高分子化合物を埋め込む工程と、前記第1の電極配線
層及びコンタクト窓の凹部に埋め込んだ導電性の有機高
分子化合物上に第2の電極配線層を被着する工程を特徴
とする半導体装置の製造方法である。
Means for Solving the Problems In order to achieve the above object, the present invention includes a step of depositing an interlayer insulating film on a semiconductor substrate, a step of forming a contact window in the interlayer insulating film, and a step of forming a contact window in the interlayer insulating film. A step of depositing a first electrode wiring layer on the partially exposed diffusion layer of the semiconductor substrate, and a step of applying a conductive organic layer to the concave portion of the first electrode wiring layer in the contact window portion by spin coating and etching back. Manufacturing a semiconductor device characterized by a step of embedding a molecular compound and a step of depositing a second electrode wiring layer on the conductive organic polymer compound buried in the first electrode wiring layer and the recessed portion of the contact window. It's a method.

作用 この半導体装置の製造方法によって、コンタクト窓の電
極配線層の平坦化が図られるとともに、電極配線抵抗を
低減することができる。
Function: By this method of manufacturing a semiconductor device, the electrode wiring layer of the contact window can be planarized and the electrode wiring resistance can be reduced.

又、コンタクト窓底部での第1の電極配線の断線は、埋
め込まれた導電性の有機高分子化合物さらには上部の第
2の電極配線層によって救済される。
Further, a break in the first electrode wiring at the bottom of the contact window is relieved by the buried conductive organic polymer compound and the second electrode wiring layer above.

実施例 以下に、第1図を参照にして本発明の半導体装置の製造
方法について詳しく説明する。
EXAMPLES Below, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to FIG.

第1図は本発明の半導体装置に於ける一実施例のコンタ
クト部分を示す断面図である。
FIG. 1 is a sectional view showing a contact portion of an embodiment of the semiconductor device of the present invention.

半導体基板11上に層間絶縁膜13としてBPSGを形
成し(b』、エッチングによう所定の個所にコンタクト
窓14を開孔した後FC+、前記コンタクト窓部分に露
出した前記半導体基板の拡散層領域12上に蒸着等によ
り第1のアルミ電極配線層15を被着し((13、前記
第1のアルミ電極配線層16の上部に導電性の有機高分
子化合物として導電性のレジスト1Bをスピン塗布によ
り被着した後(e)、エッチバックによシ第1のアルミ
電極配線層16の凹部以外の導電性のレジストを除去し
凹部にのみ導電性のレジスト18を残して埋め込んで平
坦化した後(0、前記第1のアルミ電極配線層16及び
コンタクトの凹部に埋め込んだ導電性のレジスト18上
に第2の電極配線層19を被着する(船。
After forming BPSG as an interlayer insulating film 13 on a semiconductor substrate 11 (b) and opening a contact window 14 at a predetermined location by etching, the diffusion layer region 12 of the semiconductor substrate exposed in the contact window portion is A first aluminum electrode wiring layer 15 is deposited thereon by vapor deposition or the like ((13) A conductive resist 1B is applied as a conductive organic polymer compound on top of the first aluminum electrode wiring layer 16 by spin coating. After depositing (e), the conductive resist other than the concave portions of the first aluminum electrode wiring layer 16 is removed by etch-back, and the conductive resist 18 is left only in the concave portions and buried and flattened ( 0. A second electrode wiring layer 19 is deposited on the first aluminum electrode wiring layer 16 and the conductive resist 18 embedded in the contact recess (ship).

以上のように本実施例によれば、コンタクト窓底部での
第1のアルミ配線層16が断線しても、凹部の多結晶シ
リコン及び上部の第2のアルミ配線層20によって救済
される。
As described above, according to this embodiment, even if the first aluminum wiring layer 16 is disconnected at the bottom of the contact window, it can be relieved by the polycrystalline silicon in the recessed portion and the second aluminum wiring layer 20 above.

発明の効果 本発明の半導体装置の製造方法によれば、コンタクト窓
において第1の電極配線層の上に導電性のレジストを埋
め込んで平坦化を図ることにより、電極配線抵抗を低減
するとともに、断線もなくすことができる。この結果、
電極配線層の信頼性を向上させることができる。
Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, a conductive resist is buried on top of the first electrode wiring layer in the contact window to planarize the layer, thereby reducing electrode wiring resistance and preventing disconnection. It can be eliminated. As a result,
The reliability of the electrode wiring layer can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例にかかる半導体装置のコンタ
クト部分を示す断面図、第2図は従来の半導体装置のコ
ンタクト部分を示す断面図である。 11・・・・・・半導体基板、12・・・・・・拡散層
領域、13・・・・・・層間絶縁膜、14・・・・・・
コンタクト窓、16・・・・・・第1アルミ配線層、1
6・・・・・・コンタクト周辺部の角でアルミ配線が薄
くなっている部分、1了・・・・・・コンタクト中央部
でアルミ配線が厚くな?部分、18・・・・・・導電性
のレジスト、19・・・・・・第2アルミ配線層、21
・・・・・・半導体基板、22・・・・・・拡散層領域
、23・・・・・・層間絶縁膜、24・・・・・・コン
タクト窓、26・・・・・・アルミ配線層、26・・・
・・・コンタクト周辺部の角でアルミ配線が薄くなって
いる部分、27・・・・・・コンタクト中央部でアル■
配線が厚くなる部分。
FIG. 1 is a sectional view showing a contact portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a contact portion of a conventional semiconductor device. 11... Semiconductor substrate, 12... Diffusion layer region, 13... Interlayer insulating film, 14...
Contact window, 16...First aluminum wiring layer, 1
6...The aluminum wiring is thinner at the corners around the contact, 1.Is the aluminum wiring thicker at the center of the contact? Part, 18... Conductive resist, 19... Second aluminum wiring layer, 21
... Semiconductor substrate, 22 ... Diffusion layer region, 23 ... Interlayer insulating film, 24 ... Contact window, 26 ... Aluminum wiring Layer, 26...
...The area where the aluminum wiring is thinner at the corner around the contact, 27......The aluminum at the center of the contact ■
The part where the wiring becomes thick.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に層間絶縁膜を被着する工程と、前
記層間絶縁膜にコンタクト窓を開孔する工程と、前記コ
ンタクト窓部分に露出した前記半導体基板の拡散層領域
上に第1の電極配線層を被着する工程と、コンタクト窓
部分で前記第1の電極配線層の凹部にスピン塗布及びエ
ッチバックにより導電性の有機高分子化合物を埋め込む
工程を特徴とする半導体装置の製造方法。
(1) A step of depositing an interlayer insulating film on a semiconductor substrate, a step of opening a contact window in the interlayer insulating film, and a step of depositing a first contact window on the diffusion layer region of the semiconductor substrate exposed in the contact window portion. A method for manufacturing a semiconductor device, comprising the steps of depositing an electrode wiring layer, and embedding a conductive organic polymer compound into the recessed portion of the first electrode wiring layer at the contact window portion by spin coating and etching back.
(2)前記第1の電極配線層及び導電性の有機高分子化
合物を埋め込んだコンタクト窓上に第2の電極配線層を
被着する工程を特徴とする請求項1記載の半導体装置の
製造方法。
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: (2) depositing a second electrode wiring layer on the first electrode wiring layer and the contact window in which a conductive organic polymer compound is embedded. .
(3)前記導電性の有機化合物として、導電性のレジス
トを用いることを特徴とする請求項1記載の半導体装置
の製造方法。
(3) The method of manufacturing a semiconductor device according to claim 1, wherein a conductive resist is used as the conductive organic compound.
JP15186689A 1989-06-14 1989-06-14 Manufacture of semiconductor device Pending JPH0316218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15186689A JPH0316218A (en) 1989-06-14 1989-06-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15186689A JPH0316218A (en) 1989-06-14 1989-06-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0316218A true JPH0316218A (en) 1991-01-24

Family

ID=15527941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15186689A Pending JPH0316218A (en) 1989-06-14 1989-06-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0316218A (en)

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